Abstract: A buffer having an associated state array to store the current state of the buffer. The state array includes a bit array having a number of entries, each of the entries including a status bit to indicate storage of a corresponding packet in the buffer.

Abstract: Embodiments of the invention relate to soft-pipelined state-oriented packet processing of packets received from a network. In one embodiment, a packet processor includes a packet processor core coupled to a program memory and an external memory to perform packet processing operations including defining a plurality of phases and a plurality of contexts, wherein each context includes a plurality of packets. The plurality of phases process each context. Further, a direct memory access (DMA) to the external memory is performed to obtain state data for the context being processed by the phase for use during processing by a next phase. After the last phase has processed the context, the state data is transferred back into the external memory using a final DMA transfer.

Abstract: A buffer having an associated state array to store the current state of the buffer. The state array includes a bit array having a number of entries, each of the entries including a status bit to indicate storage of a corresponding packet in the buffer.