Patents by Inventor David W. Grawrock

David W. Grawrock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411905
    Abstract: Techniques for implementing public key infrastructure using blockchains are described. An apparatus may receive, from a introducee principal, a proof-of-work. The apparatus may combine the proof-of-work with an identifier of the introducee principal. The apparatus may generate an introduction of the introducee principal. The introduction may include signing, using an asymmetric private key assigned to the apparatus, the combination of the proof-of-work and the identifier of the introducee principal. The apparatus may publish the introduction of the introducee principal to a blockchain.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, David W. Grawrock
  • Patent number: 10241842
    Abstract: Cloud container resource binding and tasking using keys is generally described herein. An example device to bind and perform tasks using cloud-based resource may include a container to claim tasks to be performed and to select and bind to a resource based on capabilities of the resource and requirements of the tasks.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, David W. Grawrock
  • Patent number: 10198333
    Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
  • Patent number: 10175994
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: James A. Sutton, II, David W. Grawrock
  • Patent number: 10042649
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: James A. Sutton, II, David W. Grawrock
  • Patent number: 10031759
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: James A Sutton, David W Grawrock
  • Patent number: 10015014
    Abstract: Technologies for secure presence assurance include a computing device having a presence assertion circuitry that receives an input seed value and generates a cryptographic hash based on the received input seed value. The computing device further verifies the integrity of the presence assertion circuitry based on the generated cryptographic hash.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: David Johnston, David W. Grawrock
  • Patent number: 9990208
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: James A. Sutton, II, David W. Grawrock
  • Publication number: 20180089001
    Abstract: Cloud container resource binding and tasking using keys is generally described herein. An example device to bind and perform tasks using cloud-based resource may include a container to claim tasks to be performed and to select and bind to a resource based on capabilities of the resource and requirements of the tasks.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Ned M. Smith, David W. Grawrock
  • Publication number: 20180006826
    Abstract: Techniques for implementing public key infrastructure using blockchains are described. An apparatus may receive, from a introducee principal, a proof-of-work. The apparatus may combine the proof-of-work with an identifier of the introducee principal. The apparatus may generate an introduction of the introducee principal. The introduction may include signing, using an asymmetric private key assigned to the apparatus, the combination of the proof-of-work and the identifier of the introducee principal. The apparatus may publish the introduction of the introducee principal to a blockchain.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Ned M. Smith, David W. Grawrock
  • Publication number: 20170364908
    Abstract: Technologies for device commissioning include a rendezvous server to receive, from a buyer device, a request to transfer ownership of a compute device to the buyer device. The rendezvous server verifies the provenance of the compute device based on a block chain and establishes a secure session with the compute device in response to verification of the provenance. The block chain identifies each transaction associated with ownership of the compute device.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Ned M. Smith, David W. Grawrock, Geoffrey H. Cooper
  • Publication number: 20170346848
    Abstract: In one embodiment, a domain controller includes: a quarantine logic to quarantine unknown devices from unrestricted network access, the quarantine logic comprising a first quarantine point at a first layer of a multi-layer communication model; a first logic to communicate with a domain name system (DNS) service to self-allocate and register a domain name with the DNS service, the domain name associated with a domain to be managed by the domain controller; a second logic to manage a group of devices of the domain; and a third logic to receive a provisioning request for a first device via an access point, wherein the access point comprises a second quarantine point at a second layer of the multi-level communication model. Other embodiments are described and claimed.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Ned M. Smith, Ravi S. Subramaniam, David W. Grawrock
  • Patent number: 9779249
    Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
  • Patent number: 9721100
    Abstract: Technologies for monitoring protected functionality of an integrated circuit device include an integrated circuit device having a protected function module. The protected function module includes a modifiable security device. When the protected function module is activated or powered up, an attribute of the modifiable security device is irreversibly modified. The integrated circuit device may be a processor, and the protected function module may be a debug module of the processor. The modifiable circuit device may be an oscillator. The frequency of the oscillator may change when the oscillator is powered due to oscillator aging. The integrated circuit device may be included in a computing device. The integrated circuit device may expose data indicative of the attribute of the modifiable security device to firmware or software of the computing device. The data may be exposed through a cryptographically signed, firmware-readable memory space. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: David W. Grawrock, Sarat Kompalli
  • Publication number: 20170147359
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 25, 2017
    Inventors: James A. Sutton, II, David W. Grawrock
  • Publication number: 20170132014
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 11, 2017
    Inventors: James A. Sutton, II, David W. Grawrock
  • Publication number: 20170115993
    Abstract: A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
    Type: Application
    Filed: January 10, 2017
    Publication date: April 27, 2017
    Inventors: James A. Sutton, II, David W. Grawrock
  • Publication number: 20170098085
    Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 6, 2017
    Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
  • Patent number: 9514028
    Abstract: An embodiment provides a level of assurance regarding correct operation of software. An embodiment creates baseline and real-time measurements of software and compares the measurements to determine whether the software is operating correctly. An application provider may include “tracing elements” in target software application. While producing the application the trace elements are detected and provide trace events, which collectively provide a “baseline trace” indicating proper application execution. The provider supplies the application and the baseline trace to a user. The user operates the application in real-time to produce a “real-time trace” based on the application still having trace elements that produce trace events (which collectively form the “real-time” trace). A comparator compares the baseline and real-time traces. If the traces are within a pre-determined range of each other the user has a level of assurance the software is operating correctly. Other embodiments are included herein.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: David W. Grawrock, Jesse Walker
  • Patent number: 9507952
    Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman