Patents by Inventor David W. Mann
David W. Mann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8493801Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: GrantFiled: August 9, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Publication number: 20120300564Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Patent number: 8284621Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: GrantFiled: February 15, 2010Date of Patent: October 9, 2012Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Publication number: 20110199843Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: ApplicationFiled: February 15, 2010Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Publication number: 20100321083Abstract: A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain.Type: ApplicationFiled: June 22, 2009Publication date: December 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Chen, William F. Lawson, David W. Mann
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Patent number: 7710144Abstract: A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.Type: GrantFiled: July 1, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, David J. Chen, William F. Lawson, David W. Mann
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Publication number: 20100001758Abstract: A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, David J. Chen, William F. Lawson, David W. Mann
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Patent number: 5121905Abstract: The present invention relates to a fail safe resilient mount which includes an outer dome shaped member having an aperture centered about an apex thereof and oppositely diposed ears extending therefrom, an inner bell shaped member axially offset from said outer member having a centered aperture at a top thereof and a locking member therein and an elastomeric material encapsulating and bonded to a domed portion of the outer member and encapsulating and bonded to the inner member and interposed between an inner surface of the outer member and an outer surface of the inner member.Type: GrantFiled: September 6, 1990Date of Patent: June 16, 1992Assignee: Karman Rubber CompanyInventors: David W. Mann, Bruce J. Senecal
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Patent number: 5044598Abstract: A resilient motor mount suitable for use as a vibrational insulating motor mount. The mount connects a motor to a support structure by using a support fixture and a motor stud separated by a flexible member. A plurality of portions of the flexible member surround the support fixture and motor stud to lessen vibrational transfer from the motor to the structure fixture and to lessen metal fatigue caused by metal to metal contact.Type: GrantFiled: August 28, 1989Date of Patent: September 3, 1991Assignee: Karman RubberInventors: David W. Mann, Bruce J. Senecal