Abstract: Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes full use of existing paths to processor registers and main storage. Control commands are distinguished from other bus communications, and executed by the control facility, to provide a full control panel function for each bus unit incorporating the control facility.

Abstract: A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has a predefined format. The assigned identification number is stored in a plurality of predefined shift register latches (SRLs) in the corresponding LSI chip to be identified. Then the LSI chip is identified by selectively reading out the stored predetermined identification number.

Abstract: The flow of work requests in a server driven process to process communication environment is described. A mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities. Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented. Management of storage in a remote processor is used to transfer work and its associated data into storage accessible by a bus unit with slave DMA capability. The slave DMA bus unit then transfers the information into storage is manages. In another way of reversing the flow, a bus unit message is used to make the original server a requestor. The bus unit message contains information which varies the request sent by the requestor. In this manner, the server, which was the original requestor transfers information using its master DMA capability flow.