Abstract: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.

Abstract: Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax2+Bx+C, thus minimizing hardware requirements.

Abstract: An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract: The division and square root systems include a multiplier. The systems also include a multipartite table system, a folding inverter, and a complement inverter, each coupled to the multiplier. The division and square root functions can be performed using three scaling iterations. The system first determines both a first and a second scaling value. The first scaling value is a semi-complement term computed using the folding inverter to invert selected bits of the input. The second scaling value is a table lookup value obtained from the multipartite table system. In the first iteration, the system scales the input by the semi-complement term. In the second iteration, the resulting approximation is scaled by a function of the table lookup value. In the third iteration, the approximation is scaled by a value obtained from a function of the semi-complement term and the table lookup value. After the third iteration, the approximation is available for rounding.

Abstract: Cellular communication systems supporting high utilization geographic regions having extensive cell overlap segments that collectively contain a substantial portion of the mobile units. A system and method for channel assignments incorporating selection from alternative transceivers defining overlapping cells is provided with load balancing to reduce call blocking. The system incorporates selective multiple handoffs responsive to channel assignment requests both to extend load balancing and also to substantially avoid call cutoff when active mobile units cross cell boundaries into possibly saturated cells.

Abstract: A multiple-layered cellular communication system particularly adapted to mobile phones and LAN type communication is provided with an overlaid arrangement of cell transceivers. By having this overlay, multiple service providers can provide a cooperative method of load sharing. The usage of the frequency spectrum can be improved and an advanced hand-off arrangement can be used to prevent or reduce the possibility of blocked calls due to cell saturation.

Abstract: An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a no-overflow condition is signaled, a subsequent plurality of iterative partial remainder computations are performed to obtain the quotient Q and remainder R with no possibility of overflow. Dividends N are characterized by a 2-bit sign field N(s1s2) formed by a first sign bit N(s1) and a second sign bit N(s2), a high order n-1 dividend magnitude bits N(himag), and a low order n-1 dividend magnitude bits N(lomag), such that N(s1) and N(himag) form a 2's complement number N(hi), while divisors D are characterized by a leading sign bit D(s) and n-1 divisor magnitude bits D(mag). Early no-overflow signaling logic uses the input dividend N and divisor D, and a 2n-1 bit first partial remainder (which has a value of [N-2.sup.

Abstract: An arithmetic circuit 10 for performing prescaled division uses a rectangular multiplier 16 and accumulator 30 operable to calculate a short reciprocal and scaled dividend and divisor to enable the sequential iterative calculation of large radix quotient digits. Each quotient digit can be calculated using a single pass through the rectangular multiplier 16 and accumulator 30 and can be accumulated to form a full precision quotient in a quotient register 36.

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder.

Abstract: A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.

Abstract: A rectangular array signed digit multiplier circuit (10) is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), an A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, and ADDER INPUT and a FEEDBACK INPUT, respectively, The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal.

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder.