Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1x mode or 2x mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

Abstract: The present disclosure provides an innovative circuit structure for control insertion into a multiple-word wide data stream. The control-insertion circuit structure is advantageously scalable as the data width increases. An exemplary implementation of the control-insertion circuit structure includes a multiple-layer shifting circuit. The multiple-layer shifting circuit has some similarities with a barrel shifter. However, unlike a barrel shifter, the multiple-layer shifting circuit moves data words in both directions and moves portions of the data to create spaces or holes in the data (rather than moving the entire width as a barrel shifter does). The output of the multiple-layer shifting circuit is a “swiss-cheese-like” structure of data, where the spaces or holes in the data are available for control insertion. Other features, aspects and embodiments are also disclosed.

Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

Abstract: The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.

Abstract: The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

Abstract: The present embodiments relate to regulating the supply voltage of an integrated circuit. The integrated circuit may implement a circuit design. The circuit design implementation may meet timing constraints with timing margins when operated with the integrated circuit at a nominal supply voltage level. The integrated circuit may further include a voltage identification controller. The voltage identification controller may determine a reduced voltage level based at least on the timing margins such that operating the circuit design implementation with the integrated circuit meets timing constraints. The voltage identification controller may direct a voltage regulator, which may be included in the integrated circuit or located outside the integrated circuit, to reduce the supply voltage level from the nominal supply voltage level to the reduced voltage level, thereby reducing the power consumption of the integrated circuit.

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

Abstract: An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits.

Abstract: A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.

Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

Abstract: In accordance with an embodiment of the invention, higher-speed outgoing data paths are used to transmit oversampled data signals, and corresponding slower-speed return data paths are used to receive return data signals. A channel-bonding control circuit measures the skew between the returned data signals and generates bit-slip and/or word-slip control signals to compensate for the skew. Transmission bit-slip (or, alternatively, clock-slip) circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers (or, alternatively, FIFO write or read enable signals) may be used to slip a whole word when the integer number of bits to slip is greater or equal to the parallel width of a lane. Various other aspects, features, and embodiments are also disclosed.

Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL.

Abstract: An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link.