Abstract: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations.

Abstract: A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

Abstract: A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).

Abstract: A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.

Abstract: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line.

Abstract: Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

Abstract: A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: A method and structure for a verification test bench system for testing an interface of a system-on-a-chip (SOC) that includes a verification interface model connected to the SOC interface and a test bench external bus interface unit (EBIU) connected to the verification interface model. The test bench EBIU is connected to a SOC EBIU within the SOC. The test bench EBIU and the SOC EBIU are mastered by the same processor in the SOC, such that the SOC interface and the verification interface model are programmed by the same test case running in the SOC.

Abstract: A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components.