Patents by Inventor David W. Price

David W. Price has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081859
    Abstract: Surgical hub systems are disclosed. A surgical hub system comprises a surgical hub configured to communicably couple to a modular device comprising a sensor configured to detect data associated with the modular device and a device processor. The surgical hub comprises a hub processor, a hub memory coupled to the hub processor. The surgical hub system also comprises a distributed control system executable at least in part by each of the device processor and the hub processor. The distributed control system is configured to: receive the data detected by the sensor; determine control adjustments for the modular device according to the data; and control the modular device according to the control adjustments. When in a first mode, the distributed control system is executed by both the hub processor and the device processor. In a second mode, the distributed control system is executed solely by the device processor.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 14, 2024
    Inventors: Frederick E. Shelton, IV, Daniel W. Price, Jason L. Harris, David C. Yates
  • Patent number: 11918302
    Abstract: An interactive control unit is disclosed. The interactive control unit includes an interactive touchscreen display, an interface configured to couple the control unit to a surgical hub, a processor, and a memory coupled to the processor. The memory stores instructions executable by the processor to receive input commands from the interactive touchscreen display located inside a sterile field and transmit the input commands to the surgical hub to control devices coupled to the surgical hub located outside the sterile field.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: March 5, 2024
    Assignee: Cilag GmbH International
    Inventors: Jeffrey D. Messerly, Peter K. Shires, Monica L. Z. Rivard, Cory G. Kimball, David C. Yates, Jeffrey L. Aldridge, Daniel W. Price, William B. Weisenburgh, II, Jason L. Harris, Frederick E. Shelton, IV, Jerome R. Morgan
  • Patent number: 11899065
    Abstract: Systems and methods for generating defect criticality are disclosed. Such systems and methods may include identifying defect results including a defect and a defect location. Such systems and methods may include receiving fault test recipes configured to test potential faults at a plurality of testing locations. Such systems and methods may include identifying a plurality of N-detect parameters based on a countable number of times the fault test recipes are configured to test a potential fault. Such systems and methods may include determining a plurality of weighting parameters based on the plurality of N-detect parameters. Such systems and methods may include generating the defect criticality for the defect based on a proximity between the plurality of testing locations and the defect location and the plurality of weighting.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: February 13, 2024
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella
  • Patent number: 11798827
    Abstract: Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: October 24, 2023
    Assignee: KLA Corporation
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, Kara L. Sherman, John Robinson
  • Patent number: 11754625
    Abstract: A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: September 12, 2023
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Robert Cappel, Oreste Donzella, Kara L. Sherman
  • Publication number: 20230280399
    Abstract: Systems and methods for generating defect criticality are disclosed. Such systems and methods may include identifying defect results including a defect and a defect location. Such systems and methods may include receiving fault test recipes configured to test potential faults at a plurality of testing locations. Such systems and methods may include identifying a plurality of N-detect parameters based on a countable number of times the fault test recipes are configured to test a potential fault. Such systems and methods may include determining a plurality of weighting parameters based on the plurality of N-detect parameters. Such systems and methods may include generating the defect criticality for the defect based on a proximity between the plurality of testing locations and the defect location and the plurality of weighting.
    Type: Application
    Filed: August 17, 2022
    Publication date: September 7, 2023
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella
  • Publication number: 20230236132
    Abstract: Systems and methods for determining a diagnosis of a screening system are disclosed. Such systems and methods include identifying defect results based on inline characterization tool data, identifying electrical test results based on electrical test data, generating one or more correlation metrics based on the defect results and the electrical test results, and determining at least one diagnosis of the screening system based on the one or more correlation metrics, the diagnosis corresponding to a performance of the screening system.
    Type: Application
    Filed: April 28, 2022
    Publication date: July 27, 2023
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella, Justin Lach, John Robinson
  • Patent number: 11656274
    Abstract: A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 23, 2023
    Assignee: KLA Corporation
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella
  • Patent number: 11624775
    Abstract: Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 11, 2023
    Assignee: KLA Corporation
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Patent number: 11614480
    Abstract: A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 28, 2023
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Patent number: 11598055
    Abstract: Applicator and method for applying melted rubber to pavement comprises a melting vat having a substantially planar bottom with a surface area, and a wide-area a heating element beneath the melting vat having a surface area more than half the surface area of the planar bottom of the melting vat and positioned beneath the melting vat. The heating element may be comprised of an aluminum oxide ceramic blanket. A double-walled construction of the vat with exhaust holes in the outer wall allows exhaust to evenly melt rubber in the vat to reduce burning of the rubber, flame blowouts, and improve fuel efficiency.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: March 7, 2023
    Inventor: David W. Price, II
  • Publication number: 20220390506
    Abstract: A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.
    Type: Application
    Filed: June 30, 2021
    Publication date: December 8, 2022
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Publication number: 20220390505
    Abstract: Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Application
    Filed: July 9, 2021
    Publication date: December 8, 2022
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, John Charles Robinson
  • Publication number: 20220359247
    Abstract: Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.
    Type: Application
    Filed: May 28, 2021
    Publication date: November 10, 2022
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella, Kara L. Sherman, John Robinson
  • Publication number: 20220307990
    Abstract: A die screening system may receive die-resolved metrology data for a population of dies on one or more samples from the one or more in-line metrology tools after one or more fabrication steps, where the die-resolved metrology data includes images generated using one or more measurement configurations of the one or more in-line metrology tools. In this way, the die-resolved metrology data provides many measurement channels per die, where a particular measurement channel includes data from a particular pixel of a particular image. The controller may then generate screening data for the population of dies from the die-resolved metrology data, where the screening data includes a subset of the plurality of measurement channels of the die-resolved metrology data, and screen the plurality of dies into two or more disposition classes including at least outlier dies based on variability in the screening data.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 29, 2022
    Inventors: John Charles Robinson, Stilian Pandev, Shifang Li, Mike Von Den Hoff, Justin Lach, Barry Saville, David W. Price, Robert J. Rathert, Chet V. Lenox, Thomas Groos, Oreste Donzella
  • Publication number: 20220260632
    Abstract: A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.
    Type: Application
    Filed: March 25, 2021
    Publication date: August 18, 2022
    Inventors: Robert J. Rathert, David W. Price, Chet V. Lenox, Oreste Donzella
  • Publication number: 20220196723
    Abstract: Automatically identifying defect-based test coverage gaps in semiconductor devices includes determining a plurality of apparent killer defects on one or more semiconductor devices with a plurality of semiconductor dies based on characterization measurements of the one or more semiconductor devices acquired by one or more semiconductor fabrication subsystems, determining at least one semiconductor die which passes at least one test based on test measurements acquired by one or more test tool subsystems, correlate the characterization measurements with the test measurements to determine at least one apparent killer defect on the at least one semiconductor die which passes the at least one test, and determining one or more gap areas on the one or more semiconductor devices for defect-based test coverage based on the at least one apparent killer defect on the at least one semiconductor die which passes the at least one test.
    Type: Application
    Filed: May 14, 2021
    Publication date: June 23, 2022
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Kara L. Sherman, Teng Song Lim, Thomas Groos, Mike Von Den Hoff, Oreste Donzella, Narayani Narasimhan, Barry Saville, Justin Lach, John Robinson
  • Patent number: 11293970
    Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 5, 2022
    Assignee: KLA Corporation
    Inventors: David W. Price, Robert J. Rathert, Kara L. Sherman, John Charles Robinson, Mike Von Den Hoff, Barry Saville, Robert Cappel, Oreste Donzella, Naema Bhatti, Thomas Groos, Teng-Song Lim, Doug Sutherland
  • Publication number: 20210239757
    Abstract: A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.
    Type: Application
    Filed: January 18, 2021
    Publication date: August 5, 2021
    Inventors: David W. Price, Robert J. Rathert, Chet V. Lenox, Robert Cappel, Oreste Donzella, Kara L. Sherman
  • Patent number: 11066792
    Abstract: Portable asphalt reclaimer having a pivotable lid with an integral heating element, and an asphalt holding chamber containing a grate. Asphalt may be reclaimed by placing asphalt chunks on the grate, heating them from above using the heating element in the lid until asphalt falls through the holes in the grate. The asphalt may be removed through a lower door. The pivotable lid may be detachable to separately heat the ground surface to which asphalt is to be applied.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: July 20, 2021
    Inventor: David W. Price, II