Abstract: A fault detection circuit monitors voltage drops associated with phase windings of a brushed or brushless reversible multi-phase motor and compares them with reference voltages to determine if the motor is out of normal operating range parameters and if a valid fault condition exists. The fault detection circuit-is included in a motor control circuit and is configurable for use with a wide variety of motors having a broad range of load characteristics. The fault detection circuit includes a programmable clock generator which generates time delays for masking faults detected during start-up and during motor phase sequencing. The fault detection circuit thereby avoids transient and spurious faults and prevents the unnecessary termination of motor operation. The length of the mask time delay required for effective fault detection operation depends on the load characteristics of the selected motor.

Abstract: An output of a power-on-reset (POR) circuit is coupled to another circuit which needs to have the logic states thereof reset during each time a power supply used to power same is switched on. The POR circuit includes a first input circuit for generating an output signal that tracks the power supply output voltage Vdd approximately a first predetermined threshold below Vdd, as Vdd ramps up and further includes a second input circuit which generates an output signal which tracks approximately a second predetermined threshold above a second fixed voltage level, e.g., ground. The POR circuit further includes a comparator which compares the output signals from the first and second input circuits and switches an output signal thereof from a first to a second logic state once the input circuit output signals cross each other. A buffer is typically coupled to the output of the comparator to limit loading on same so as not to affect the comparator switching point.