Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

Abstract: Barrier film with a high colorless transparency comprising a flexible plastic substrate. A barrier layer is formed on the surface and has a thickness ranging from approximately 50 to less than 200 Angstroms and is formed of a material selected from the group of aluminum oxide, tin oxide and yttrium oxide. An additional barrier layer formed of silicon dioxide may also be formed on the barrier layer.

Abstract: Barrier film with a high colorless transparency comprising a flexible plastic substrate. A barrier layer is formed on the surface and has a thickness ranging from approximately 50 to less than 200 Angstroms and is formed of a material selected from the group of aluminum oxide, tin oxide and yttrium oxide. An additional barrier layer formed of silicon dioxide may also be formed on the barrier layer.

Abstract: Barrier film with a high colorless transparency comprising a flexible plastic substrate. A barrier layer is formed on the surface and has a thickness ranging from approximately 50 to less than 200 Angstroms and is formed of a material selected from the group of aluminum oxide, tin oxide and yttrium oxide. An additional barrier layer formed of silicon dioxide may also be formed on the barrier layer.

Abstract: The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.

Abstract: Barrier film with a high colorless transparency comprising a flexible plastic substrate. A barrier layer is formed on the surface and has a thickness ranging from approximately 50 to 100 Angstroms and is formed of a material selected from the group of aluminum oxide, tin oxide and yttrium oxide. An additional barrier layer formed of silicon dioxide may also be formed on the barrier layer.

Abstract: Method for providing a patterned thin film on a flexible web-like substrate having at least one surface. A patterned release coating which carries the desired pattern is deposited on the surface and has openings therein through which the surface of the substrate is exposed. A thin film is deposited over the patterned release coat and onto the portions of the surface exposed through the openings. The patterned release coating is then removed and the thin film portions carried thereby to provide a patterned thin film on the substrate.

Abstract: Method for providing a patterned thin film on a flexible web-like substrate having at least one surface. A patterned release coating which carries the desired pattern is deposited on the surface and has openings therein through which the surface of the substrate is exposed. A thin film is deposited over the patterned release coat and onto the portions of the surface exposed through the openings. The patterned release coating is then removed mechanically along with the thin film portions carried thereby to provide a patterned thin film on the substrate. The mechanical removal may be accomplished by advancing the coated substrate through a solvent while brushing the substrate, subjecting the substrate to high velocity air, or contacting the substrate with the adhesive layer of a web.

Abstract: Tamper evident optical device comprising a substrate and a multi-layer taper evident splittable coating carried by the substrate. The coating has a release region formed therein. An adhesive is secured to the tamper evident coating.