Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A plurality of feed-throughs are provided on the non-volatile memory die to provide communication paths from the processor die to package pads which are in the shadow of the non-volatile memory die relative to the processor die and thus prevent direct connection from the processor die to the package pad. In normal run mode, these pads are exclusively used as feed-through, providing a direct connection between a specific pad on the processor die and a specific pad on the package.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor includes an in-system programming mode including first and second memory interface control registers on the processor die and the memory die, respectively, for receiving control bits from the processor core for controlling multiplexers on the dies. The various bit output lines of the first memory interface control register are coupled to the control inputs of the multiplexers.

Abstract: An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.The processor can be programmed internally or externally. In the in-system programming mode, the processor program counter is used to fetch running instructions out of an on-board ROM instruction memory on the processor die. The processor core outputs an address into which data is to be programmed on its output data bus. The processor core then receives from an external device the data which is to be programmed into the selected address and outputs it serially onto the data bus and therefrom to the memory die.