Patents by Inventor David W. Winston
David W. Winston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8825455Abstract: An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.Type: GrantFiled: November 4, 2011Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Calvin J. Bittner, Peter Feldmann, Richard D. Kimmel, Tong Li, Ali Sadigh, David W. Winston
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Publication number: 20140129202Abstract: Before supplying a series of instructions to a circuit simulator, methods and systems cache the series of instructions and partition the series of instructions into an active portion and an inactive portion. Instead of supplying the entire series of instructions to the circuit simulator, the methods and systems supply only the instructions directed to the active portion of the integrated circuit to the circuit simulator. Thus, the circuit simulator creates a reduced circuit simulation from just the instructions directed to the active portion (instead of a full integrated circuit that would have been simulated with the entire series of instructions). The reduced circuit simulated by these systems and methods has less circuit elements relative to any integrated circuit that would have been simulated with the entire series of instructions. Thus, this reduced circuit is only a portion of the integrated circuit that would have been simulated.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Sadigh, David W. Winston
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Patent number: 8655634Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.Type: GrantFiled: March 10, 2010Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston
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Publication number: 20130116985Abstract: An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.Type: ApplicationFiled: November 4, 2011Publication date: May 9, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Calvin J. BITTNER, Peter FELDMANN, Richard D. KIMMEL, Tong LI, Ali SADIGH, David W. WINSTON
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Patent number: 8239794Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.Type: GrantFiled: September 29, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Bhavna Agrawal, David J. Hathaway, Pravin P. Kamdar, Karl K. Moody, III, Peng Peng, David W. Winston
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Patent number: 8037433Abstract: A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.Type: GrantFiled: August 22, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Tong Li, Richard Q. Williams, David W. Winston
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Publication number: 20110224965Abstract: A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston
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Publication number: 20110077882Abstract: Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit.Type: ApplicationFiled: September 29, 2009Publication date: March 31, 2011Applicant: International Business Machines CorporationInventors: Bhavna Agrawal, David J. Hathaway, Pravin P. Kamdar, Karl K. Moody, III, Peng Peng, David W. Winston
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Publication number: 20100050138Abstract: A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Applicant: International Business Machines CorporationInventors: Dureseti Chidambarrao, Tong Li, Richard Q. Williams, David W. Winston