Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a particular duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve switching conditions in a closed loop system. An example device includes a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled the first switch, and wherein the second terminal is coupled to the second switch, a first multiplier coupled to the first terminal and to the second terminal, wherein the first multiplier is adapted to be coupled to at least a third node and a fourth node, and a second multiplier coupled to the first terminal and to the second terminal.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve switching conditions in a closed loop system. An example device includes a first switch adapted to be coupled to a first node, a second switch adapted to be coupled to a second node, a capacitor including a first terminal and a second terminal, wherein the first terminal is coupled the first switch, and wherein the second terminal is coupled to the second switch, a first multiplier coupled to the first terminal and to the second terminal, wherein the first multiplier is adapted to be coupled to at least a third node and a fourth node, and a second multiplier coupled to the first terminal and to the second terminal.

Abstract: Methods and apparatus for DC-DC soft start are disclosed herein, an example DC-DC voltage converter includes at least two transistors to at least charge or discharge an inductor from an input source and to ground respectively, the inductor to output an output voltage. A synchronize and track circuit generates a bias current based on a reference voltage. An amplifier generates an error current based on an output voltage and the reference voltage. An oscillator oscillates at a switching frequency based on the bias current and the error current. A multiplexer selects between (1) a first input signal generated based on the switching frequency, and (2) a second input signal generated based on the switching frequency and the error current, for output as a reset signal. A latch provides a control signal to the at least two transistors based on the reset signal and the switching frequency.

Abstract: Methods and apparatus for flying capacitor balancing in multilevel converters are disclosed. Example flying capacitor balancing circuitry can include voltage difference sense and control circuitry and duty cycle timing adjustment circuitry. The voltage difference sense and control circuitry can generate a compensation control signal for the duty cycle timing adjustment circuitry.

Abstract: Systems and methods of driving multiple outputs are provided in which a single inductor may be used to drive multiple output such as independent strings of LEDs or white LEDs (WLEDs). In an example embodiment, a boost DC to DC converter may be used with a single inductor to drive multiple outputs. In an example embodiment, the error voltage of each of the multiple outputs is sampled during each cycle of the DC to DC converter and the largest error voltage is determined for that cycle. Power from the DC to DC converter is then supplied to that output during that cycle.

Abstract: Systems and methods of driving multiple outputs are provided in which a single inductor may be used to drive multiple output such as independent strings of LEDs or white LEDs (WLEDs). In an example embodiment, a boost DC to DC converter may be used with a single inductor to drive multiple outputs. In an example embodiment, the error voltage of each of the multiple outputs is sampled during each cycle of the DC to DC converter and the largest error voltage is determined for that cycle. Power from the DC to DC converter is then supplied to that output during that cycle.