Abstract: An LDO regulator includes two linear regulator circuits and an internal priority logic scheme that favors generating a regulated output voltage using a regulated supply voltage over an unregulated supply voltage. The unregulated supply voltage is applied to a first input terminal from a raw voltage source. The regulated supply voltage is applied to a second input terminal from, for example, a switching (e.g., BUCK) regulator. Two output devices are respectively connected between the first and second input terminals and the LDO output terminal. The first regulator circuit causes the first output device to supply the desired regulated output voltage while the switching regulator ramps up. Once the regulated supply voltage is high enough to allow regulation, the internal priority logic scheme disables the first regulator circuit, whereby the desired regulated output voltage is generated solely by the second regulator circuit through the second output device.

Abstract: An LDO regulator includes two linear regulator circuits and an internal priority logic scheme that favors generating a regulated output voltage using a regulated supply voltage over an unregulated supply voltage. The unregulated supply voltage is applied to a first input terminal from a raw voltage source. The regulated supply voltage is applied to a second input terminal from, for example, a switching (e.g., BUCK) regulator. Two output devices are respectively connected between the first and second input terminals and the LDO output terminal. The first regulator circuit causes the first output device to supply the desired regulated output voltage while the switching regulator ramps up. Once the regulated supply voltage is high enough to allow regulation, the internal priority logic scheme disables the first regulator circuit, whereby the desired regulated output voltage is generated solely by the second regulator circuit through the second output device.

Abstract: A voltage regulator includes a voltage divider connected between a soft-start pin and the voltage regulator's error amplifier. The voltage divider has the same divider ratio as that of the voltage regulator's feedback voltage divider, which is used to divide the regulated output voltage fed back to the error amplifier. To facilitate soft-start operations, an external, user-supplied capacitor is connected to the soft-start pin. To facilitate voltage tracking operations, a predetermined master supply voltage is applied to the soft-start pin.

Abstract: A voltage regulator including a bandgap control circuit that maintains the regulator's bandgap voltage at a predetermined voltage level after an externally generated enable signal is de-asserted until the regulated output voltage has dropped below a predetermined low reference voltage. The bandgap control circuit includes a latch that is set by the enable control signal to generate a bandgap control signal, which is used to activate a bandgap reference generator that generates the bandgap voltage. The latch is reset to de-assert the bandgap control signal by a logic gate and a low output voltage detector. The detector generates a low output voltage detection signal when the regulated output voltage falls below a low reference voltage. The logic gate generates a rising edge signal that resets the latch only when the enable signal is de-asserted and the detector generates the detection signal, thereby preventing unintended shutdown of the bandgap reference generator.

Abstract: A digital video signal processing system monitors the rate of change of the digital video signal to detect large rates of change that indicate the presence of an object edge in the video image. Upon detection of such an edge, the digital signal is sampled at a variable rate so that more sampling is performed immediately before and after the sudden change in the signal and less sampling is performed during the change. The result is that the edge in the video image occupies less pixels and, therefore, is more clear and defined that would be the case otherwise. Consequently, the appearance of the video image is enhanced. This can be considered as the digital analogue of analog H-sweep velocity modulation.

Abstract: Standard definition video can be upconverted to high-definition video without degrading the appearance of edges, lines and other visual transitions in the image with a diagonal geometry. Each horizontal scan line of the video is monitored to identify the location of such visual transitions. The transitions are then matched in successive scan lines. Successive scan lines are then morphed, e.g., shifted forward or backward to move the transition in each line toward an average position for the transition as located in the two successive scan lines. The successive morphed lines are then added to produce a single interpolated line that is interlaced between its parent lines in a resulting high-definition video signal.

Abstract: A digital video signal processing system monitors the rate of change of the digital video signal to detect large rates of change that indicate the presence of an object edge in the video image. Upon detection of such an edge, the digital signal is sampled at a variable rate so that more sampling is performed immediately before and after the sudden change in the signal and less sampling is performed during the change. The result is that the edge in the video image occupies less pixels and, therefore, is more clear and defined that would be the case otherwise. Consequently, the appearance of the video image is enhanced. This can be considered as the digital analogue of analog H-sweep velocity modulation.

Abstract: Standard definition video can be upconverted to high-definition video without degrading the appearance of edges, lines and other visual transitions in the image with a diagonal geometry. Each horizontal scan line of the video is monitored to identify the location of such visual transitions. The transitions are then matched in successive scan lines. Successive scan lines are then morphed, e.g., shifted forward or backward to move the transition in each line toward an average position for the transition as located in the two successive scan lines. The successive morphed lines are then added to produce a single interpolated line that is interlaced between its parent lines in a resulting high-definition video signal.