Abstract: A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

Abstract: Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

Abstract: A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

Abstract: A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

Abstract: Structures and methods herein insert one or more parallel “recessive nulling” driver impedances across a controller area network (CAN) bus starting at the time of a dominant-to-recessive data bit transition and extending for a selected recessive nulling time period. Doing so increases a rate of decay of a CAN bus dominant-to-recessive differential signal waveform, permits a shortened recessive bit time period, and allows for increased CAN bus bandwidth. Various modes of operation are applicable to various CAN bus node topologies. Recessive nulling may be applied to only the beginning portion of a recessive bit following a dominant bit (“LRN mode”) or to the entire recessive bit time (“HRN mode”). And, some embodiments may apply LRN operations to some recessive CAN frame bits and HRN operations to others.

Abstract: A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

Abstract: Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

Abstract: Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.