Patents by Inventor David Webber

David Webber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250050376
    Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.
    Type: Application
    Filed: February 5, 2024
    Publication date: February 13, 2025
    Applicant: NanoClear Technologies, Inc.
    Inventors: Harold Franklin GREER, Rehan KAPADIA, Angelica SAENZ, David WEBBER
  • Patent number: 11890640
    Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 6, 2024
    Assignee: Nanoclear Technologies, Inc.
    Inventors: Harold Frank Greer, Rehan Kapadia, Angelica Saenz, David Webber
  • Publication number: 20230095274
    Abstract: Methods of forming a monolayer of nanoparticles are described. The method may include forming an activated surface on a substrate. Methods may also include contacting the activated surface with a fluid including nanoparticles. Methods may further include forming a plurality of monolayers in the liquid on the activated surface. The plurality of nanoparticles may include a first monolayer of nanoparticles bonded to the activated surface. The plurality of nanoparticles may include a second monolayer of nanoparticles bonded to the first monolayer of nanoparticles. The bond strengths between a nanoparticle and the underlying substrate, between adjacent nanoparticles, and between nanoparticles of adjacent monolayers may be related by a specific relationship. The method may also include removing monolayers of the plurality of monolayers while retaining the first monolayer to form the substrate with the first monolayer. Systems for performing the methods and substrates resulting from the methods are also described.
    Type: Application
    Filed: January 21, 2021
    Publication date: March 30, 2023
    Inventors: Harold Frank GREER, Rehan KAPADIA, Angelica SAENZ, David WEBBER
  • Publication number: 20150143294
    Abstract: A system and method for presenting a scrollable-list interface comprising defining an ordered set of elements which includes elements classified into at least two layers; rendering a set of first layer elements of the ordered set in a navigable interface, the set of first layer elements ordered according to the ordered set; rendering a condensed indicator element associated with at least one element classified in a second layer in the navigable interface, the condensed indicator element ordered within the set of first layer elements according to the ordered set; receiving a user input to the navigable interface; and augmenting a layered representation of the ordered set in the navigable interface, wherein the layered representation is augmented in accordance with the user input.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 21, 2015
    Inventors: Mathew Piccinato, Gregory Schwartz, Christopher Kaufman, David Webber, Jesse Hendrickson
  • Publication number: 20150035685
    Abstract: A system for alerting a user includes a first device for vehicle-to-pedestrian communication. The first device is operable by a pedestrian. The system further includes a vehicle operable by a driver including a second device for vehicle-to-pedestrian communication. The system is configured to provide an alert via at least one of the first device and second device to at least one of the driver and the pedestrian.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 5, 2015
    Inventors: Richard Dean Strickland, Meng Yuan, Sue Bai, David Webber, Radovan Miucic
  • Patent number: 8434051
    Abstract: A method of automating circuit design is provided and includes storing one or more circuit design schematics in a memory, providing, by way of an interface, a plurality of search parameters for searching for nets of the schematics in the memory, searching for nets of the schematics in the memory in accordance with search parameters input into the interface and presenting, by way of the interface, information associated with a net matching the received search parameters.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kutalmis Koyuncu, David Webber, Michael H. Wood
  • Publication number: 20110066996
    Abstract: A method of automating circuit design is provided and includes storing one or more circuit design schematics in a memory, providing, by way of an interface, a plurality of search parameters for searching for nets of the schematics in the memory, searching for nets of the schematics in the memory in accordance with search parameters input into the interface and presenting, by way of the interface, information associated with a net matching the received search parameters.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kutalmis Koyuncu, David Webber, Michael H. Wood
  • Patent number: 7146520
    Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Billeci, Timothy G. McNamara, Ching-Lung L. Tong, David Webber
  • Publication number: 20060184773
    Abstract: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.
    Type: Application
    Filed: February 11, 2005
    Publication date: August 17, 2006
    Inventors: Brian Curran, Ashutosh Goyal, Michael Vaden, David Webber
  • Publication number: 20050278572
    Abstract: A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 15, 2005
    Applicant: International Business Machines Corp.
    Inventors: Fadi Busaba, Lawrence Powell, Martin Schmookler, Michael Vaden, David Webber
  • Publication number: 20040230857
    Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 18, 2004
    Applicant: International Business Machines Corporation
    Inventors: Michael Billeci, Timothy G. McNamara, Ching-Lung L. Tong, David Webber
  • Patent number: 6780224
    Abstract: Method and apparatus for treatment of air conditioning systems and the like provides an air treatment element (18) comprising a microbial control medium and an entrainment medium therefor. The air treatment element (18) is adapted to be placed on the upstream side of the air cooling element (14) of an air conditioning system so that the air stream (16) thereto has entrained therein droplets of entrainment medium (32) containing the microbial treatment medium which are then condensed on the cooling surfaces, thereby removed from the air stream (16) and effectively applied to all relevant surfaces for exerting an effective microbial control action.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: August 24, 2004
    Assignee: Universal Master Products Limited
    Inventors: Harry Banham, David Webber
  • Patent number: D1097077
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: October 7, 2025
    Assignee: SOUTHPAW INDUSTRIES P/L
    Inventors: Simon Andresen, Marc Fraser, David Webber