Abstract: In several embodiments of the invention, a programmable architecture for FIR filters includes a tapped delay chain and a number of different slices. Each slice has a multiplexer that receives all of the tapped input-signal samples and a programmable current driver. Each slice can be independently programmed to correspond to any one of the taps in the delay chain, such that zero, one, or more slices can be associated with any of the delay-chain taps. Moreover, the current driver in each slice can be independently programmed to contribute any available driver strength level for the selected tap, where the combination of one or more drive strengths associated with a given tap corresponds to the effective tap coefficient for that tap. In this way, the architecture can be programmed to provide a variety of different filters having not just transfer functions with different coefficient values, but also transfer functions having different numbers of pre-cursor and/or post-cursor taps.

Abstract: A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional.

Abstract: A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: A combination battery charger is disclosed to include a housing, a first electric plug pivoted to the housing for connection to the electric socket for cigarette lighter of a motor vehicle and turnable in and out of a first outside open chamber of the housing within the range of 0 to 180° to fit different installation angles, a second electric plug pivoted to the housing for connection to a city power supply outlet and turnable in and out of a second outside open chamber of the housing, and a charging circuit board mounted inside the housing and electrically connected to the first electric plug and the second electric plug for converting city power supply/car battery power supply into a charging power supply for charging a battery being inserted into a third outside open chamber of the housing and set into contact with metal contacts of the charging circuit board that are suspended in the third outside open chamber.

Abstract: A computer aided wave-shaped circuit line drawing method and system is proposed, which is designed for use with a computer platform for providing a user-operated wave-shaped circuit line drawing function, and which is characterized by the utilization of computer-aided graphic drawing technology to allow a user to define a set of dimensional attributes for a wave-shaped microstrip line, and whereby the shape of the wave-shaped microstrip line will be automatically drawn on a circuit layout diagram. Compared to the prior art, since the invention allows the dimensional attributes and locations of each constituent portions (i.e., segments and turning points) in the wave-shaped microstrip to be precisely drawn on the circuit layout diagram, it allows the realization of a microwave digital circuit board from the circuit layout diagram to have precise characteristic impedance and thus precise electrical performance in actual operation.

Abstract: A video monitoring device is constructed to include a casing formed of a hollow bottom shell and a top cover, which covers the bottom shell and is horizontally rotatable on the bottom shell, a camera turnable about a horizontal pivot at the top cover, and a driver mounted inside the bottom shell and controlled to rotate the top cover and the camera horizontally on the bottom shell and to turn the cameral vertically about the horizontal pivot.

Abstract: A camera platform assembly is disclosed and claimed to include a control base adapted to receive control signal, a rotary table horizontally rotatably supported on the control base and controlled to rotate horizontally on the control base by control signal received by the control base, and movable rack pivoted to the rotary table and adapted to carry a camera and to adjust the angle of inclination of the camera.

Abstract: An integrated plasmon detector includes a top layer of material adapted to generate a plasmon when excited by a beam of light incident onto a surface of the top layer, an interface layer joined to the top layer opposite from the surface of the top layer and adapted to slow polarons emitted by the plasmon to thermal electrons, and a collector layer joined to the interface layer opposite from the top layer and adapted to collect the thermal electrons from the interface layer.

Abstract: An air platen assembly is described and includes a platen that has a plurality of concentric rings. Each of the rings has a plurality of openings in order to provide a cushion of air to a CMP belt. At least one of the rings extends beyond an outer edge of a wafer to be planarized by the CMP belt. A support is attached with the platen and has a plurality of air ports for pressurized air to pass to the rings of the platen. A gasket is positioned between the support and the platen and has a plurality of cutouts that align with the openings and the air ports. A base is also included and supports the support.

Abstract: The invention provides a congestion control scheme that is a delay based scheme that includes a scalable queue size and one-way queueing delay measurement to reduce network congestion. Queue size is managed by queue control, a scalable utility function, dynamic alpha tuning, and/or randomized alpha tuning. One-way queueing delay is accomplished by measuring backward queueing delay management using various methods of estimating the receiver clock period. Embodiments include estimating the receiver clock period using single sample and multiple sample periods. The system includes a method for detecting route change.

Abstract: A method for monitoring the surface roughness of a metal, comprises impinging a laser beam onto the surface of a metal layer to induce the formation of a plasmon therein, and monitoring a current of decay electrons emitted by the plasmon.

Abstract: A method for making a semiconductor device is provided. The method includes forming transistor structures on a substrate and forming interconnect metallization structures in a plurality of levels through depositing a sacrificial layer. A dual damascene process is performed to etch trenches and vias, and filling and planarizing the trenches and vias. The sacrificial layer is etched throughout the plurality of levels of the interconnect metallization structures, thus leaving a voided interconnect metallization structure. The voided interconnect metallization structure is filled with low K dielectric material, thus defining a low K dielectric interconnect metallization structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having transistor devices and a plurality of copper interconnect metallization lines and conductive vias. The plurality of copper interconnect metallization lines and conductive vias are defined in each of a plurality of interconnect levels of the semiconductor device such that the plurality of copper interconnect metallization lines and conductive vias are isolated from each other by an air dielectric. The semiconductor device further includes a plurality of supporting stubs each of which is configured to form a supporting column that extends through the plurality of interconnect levels of the semiconductor device.

Abstract: A chemical mechanical planarization (CMP) system is provided. The system includes a polishing surface and a platen disposed along an underside of the polishing surface. A retaining ring surrounds the platen. The retaining ring includes a lower annular sleeve and an upper annular sleeve moveably disposed over the lower annular sleeve. A method for reducing a consumption of compressed dry air (CDA) during a chemical mechanical planarization (CMP) operation is also described.