Abstract: Hybrid analog-digital processors and related methods are described. A hybrid analog-digital processor or related method may carry out an algorithm for efficiently performing a Fourier Transform with lower power consumption and higher speed compared with fully-digital processors. A hybrid analog-digital processor or related method may use a digital processor to perform some portions of a Fourier Transform, such as sizing signals for input into an analog accelerator (such as a photonic accelerator). The analog accelerator may be configured to perform some portions of the Fourier Transform by performing matrix-vector multiplication on the sized signals using light. Further efficiency may be provided by in some environments by batching signals that are input into the analog accelerator into 2D arrays, or by performing matrix-vector multiplication using a submatrix of a full Fourier Transform matrix.

Abstract: Described herein are techniques of training a machine learning model and performing inference using an analog processor. Some embodiments mitigate the loss in performance of a machine learning model resulting from a lower precision of an analog processor by using an adaptive block floating-point representation of numbers for the analog processor. Some embodiments mitigate the loss in performance of a machine learning model due to noise that is present when using an analog processor. The techniques involve training the machine learning model such that it is robust to noise.