Patents by Inventor David William Boerstler
David William Boerstler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8736304Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.Type: GrantFiled: June 30, 2005Date of Patent: May 27, 2014Assignees: International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: David William Boerstler, Eskinder Hailu, Kazuhiko Miki, Jieming Qi
-
Patent number: 8201112Abstract: A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs.Type: GrantFiled: May 29, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: David William Boerstler, Jieming Qi
-
Patent number: 8054119Abstract: The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.Type: GrantFiled: April 19, 2005Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
-
Patent number: 8041537Abstract: Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.Type: GrantFiled: June 27, 2008Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Jieming Qi, Eskinder Hailu, David William Boerstler, Masaaki Kaneko
-
Patent number: 7917795Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.Type: GrantFiled: January 15, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Byron Lee Krauter, Kazuhiko Miki, Jieming Qi
-
Patent number: 7890561Abstract: A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.Type: GrantFiled: August 16, 2005Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
-
Patent number: 7863958Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.Type: GrantFiled: December 31, 2008Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: David William Boerstler, Steven Mark Clements, Jieming Qi
-
Patent number: 7831006Abstract: An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.Type: GrantFiled: June 4, 2008Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
-
Patent number: 7809974Abstract: A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.Type: GrantFiled: January 16, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Mack Wayne Riley, Michael Fan Wang
-
Patent number: 7789558Abstract: Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.Type: GrantFiled: March 11, 2009Date of Patent: September 7, 2010Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Munehiro Yoshida, David William Boerstler
-
Patent number: 7760843Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.Type: GrantFiled: August 7, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
-
Publication number: 20100164580Abstract: A clock signal duty cycle adjustment circuit includes a duty cycle correction circuit that receives a clock input signal that may need duty cycle correction. The duty cycle correction circuit may derive first and second differential clock signals from the clock input signal. The first and second differential clock signals may exhibit respective voltage offsets. The duty cycle correction circuit includes a voltage offset shift circuit that may shift the voltage offset that one of the first and second differential clock signals exhibits to adjust the effective duty cycle of a clock output signal. The duty cycle adjustment circuit derives the clock output signal from the voltage offset adjusted first and second differential clock signals in response to a duty cycle error signal.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM CorporationInventors: David William Boerstler, Steven Mark Clements, Jieming Qi
-
Patent number: 7747892Abstract: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal.Type: GrantFiled: February 25, 2008Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Kazuhiko Miki, Jieming Qi
-
Patent number: 7716516Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.Type: GrantFiled: June 21, 2006Date of Patent: May 11, 2010Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.Inventors: Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu, Byron Lee Krauter, Stephen Douglas Weitzel, Jieming Qi, Kazuhiko Miki, David William Boerstler, Gilles Gervais, Kirk David Peterson, Robert Walter Berry, Jr., Sang Hoo Dhong
-
Patent number: 7701269Abstract: A circuit for managing voltage swings across FETs comprising a reference precision resistor, a first FET and a second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first FET and the third FET maintain a linear relationship with respective drain to source voltages of the first FET and the third FET.Type: GrantFiled: May 29, 2008Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Jieming Qi
-
Patent number: 7698588Abstract: The present invention discloses, in one aspect, a synchronizing circuit for synchronizing transmitted data. In one embodiment, the synchronization technique comprises a subsystem configured to compare positive and negative transitions of a core clock signal with positive and negative transitions of a source clock signal to determine a relationship between the transitions of the core clock signal and positions of the negative transitions of the source clock signal. The synchronization circuit also comprises logic circuitry coupled to the subsystem and configured to generate a final sampling signal based on the relationship. In addition, the synchronization circuit comprises a data sampler coupled to the logic circuitry and configured to sample a source data signal synchronized with the source clock signal using the final sampling signal, and to generate a core data signal synchronized with the core clock signal based on the sampling.Type: GrantFiled: May 15, 2003Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Chulwoo Kim, Stephen Douglas Weitzel
-
Patent number: 7692460Abstract: A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.Type: GrantFiled: May 29, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Jieming Qi
-
Patent number: 7646177Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.Type: GrantFiled: December 31, 2008Date of Patent: January 12, 2010Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Jieming Qi
-
Publication number: 20090322311Abstract: Embodiments of the disclosure provide systems and methods for using a PLL and a high frequency generator outside the loop to obtain the fmax of the divider. The divider in the PLL loop is fed by a VCO and its operation range is characterized by measuring the PLL lock range. An identical copy of the same divider is used outside the PLL loop and it is fed by a higher frequency clock. The high frequency clock is generated by the multiple phase of the VCO. By characterizing the outputs from both dividers, the fmax of the divider is obtained.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Inventors: Jieming Qi, Eskinder Hailu, David William Boerstler, Masaaki Kaneko
-
Publication number: 20090326862Abstract: Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Inventors: Jieming Qi, Eskinder Hailu, David William Boerstler, Masaaki Kaneko