Abstract: A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor.

Abstract: A method and apparatus for improving the efficiency of hardware-based binary multiplication. By using radix-32 and radix-256 multipliers where each radix-32 digit is represented by two radix-7 digits and each radix-256 digit is represented by three radix-11 digits, the digit magnitudes are in power of two, which simplifies the implementation of the partial product generation. The partial products depending on multiples of the radices 7 or 11 can be separately accumulated, with multiplication by the radix a pre- or post-computation option.

Abstract: A bipartite compression technique is used to implement a bipartite reciprocal table that provides seed reciprocal values for multiplicative (reciprocal refinement) division. The bipartite reciprocal table (12) includes component tables P and N. The input table index is partitioned into high, middle, and low order parts ?x.sub.h .vertline.x.sub.m .vertline.x.sub.1 !'the high and middle order parts ?x.sub.h .vertline.x.sub.m ! index the P Table, and the high and low order parts ?x.sub.h .vertline.x.sub.1 ! index the N Table. The P and N Tables provide first and second component outputs which form a redundant output from the bipartite lookup table. The bipartite table output may be (a) optimal in that, for each entry in each table, the maximum relative error is the minimum possible, and/or (b) when fused with rounding, faithful (i.e., accurate to one unit in the last place).

Abstract: A system for the early detection of overflow or exceptional quotient/remainder pairs is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--if early overflow is not signaled, and if an exceptional quotient/remainder pair is not detected, a quotient Q and remainder R are obtained by successive iterative partial remainder computations, which may be performed with no possibility of overflow. The detection system uses only the divisor, dividend, and first partial remainder. Early overflow detection uses three tests (FIGS. 2a, 2b, 2c): an exceptional divisor test, an exceptional dividend test, and an exceptional quotient test. Early exceptional quotient/remainder pair detection provides, when overflow is not signaled, exceptional quotient/remainder pairs using the exceptional divisor test for the exceptional divisor -2.sup.n-1 (FIG. 2c) and the exceptional quotient test for the exceptional quotient -2.sup.n-1 (FIG. 2b).

Abstract: A numeric processor includes a multiply-add circuit with redundant value interface circuitry for performing mathematical function computations as a succession of product sums using redundant binary format values (such as signed digit) as the multiplicand and/or the addend inputs to the multiply-add circuit. The redundant value interface circuitry (i) extracts a predetermined number of bits from a redundant product sum to form a redundant truncated product sum, and (ii) couples the redundant truncated product sum to either, or both, multiplicand and addend inputs. In this manner, successive redundant product sums are calculated using without conversion to nonredundant binary format. In a preferred embodiment, the numeric processor includes a single multiply-add circuit, with redundant truncated product sum values being fed back to the multiplicand and/or addend inputs.