Patents by Inventor David Wolk Mendel
David Wolk Mendel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11349587Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.Type: GrantFiled: March 30, 2018Date of Patent: May 31, 2022Assignee: Intel CorporationInventors: Nigel Antoine Gulstone, David Wolk Mendel, Sita Rama Chandrasekhar Mallela, Rajiv Dattatraya Kane
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Publication number: 20190044637Abstract: Particular embodiments described herein provide for an electronic device that can be configured to determine that a packet needs a timestamp, determine an initial timestamp for a reference block, communicate the reference block to a monitor engine, receive an asynchronous pulse from the monitor engine after the monitor engine received the reference block, determine a synchronization timestamp for the asynchronous pulse, and determine the timestamp for the packet based on the initial timestamp for the reference block and the synchronization timestamp for the asynchronous pulse.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Nigel Antoine Gulstone, David Wolk Mendel, Sita Rama Chandrasekhar Mallela, Rajiv Dattatraya Kane
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Patent number: 6815981Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: GrantFiled: February 6, 2003Date of Patent: November 9, 2004Assignee: Altera CorporationInventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
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Publication number: 20030128051Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: ApplicationFiled: February 6, 2003Publication date: July 10, 2003Inventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
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Publication number: 20030016053Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: ApplicationFiled: April 8, 2002Publication date: January 23, 2003Inventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
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Patent number: 6490717Abstract: A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a “sub-netlist” within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.Type: GrantFiled: August 15, 2000Date of Patent: December 3, 2002Assignee: Altera CorporationInventors: Bruce Pedersen, Francis B. Heile, Marwan Adel Khalaf, David Wolk Mendel
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Patent number: 6392438Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.Type: GrantFiled: October 6, 2000Date of Patent: May 21, 2002Assignee: Altera CorporationInventors: Richard G. Cliff, Srinivas T. Reddy, David Edward Jefferson, Rina Raman, L. Todd Cope, Christopher F. Lane, Joseph Huang, Francis B. Heile, Bruce B. Pedersen, David Wolk Mendel, Craig Schilling Lytle, Robert Richard Noel Bielby, Kerry Veenstra
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Patent number: 6134705Abstract: A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a "sub-netlist" within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.Type: GrantFiled: October 27, 1997Date of Patent: October 17, 2000Assignee: Altera CorporationInventors: Bruce Pedersen, Francis B. Heile, Marwan Adel Khalaf, David Wolk Mendel
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Patent number: 6102964Abstract: A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design." The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions.Type: GrantFiled: October 27, 1997Date of Patent: August 15, 2000Assignee: Altera CorporationInventors: John Tse, Fung Fung Lee, David Wolk Mendel
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Patent number: 6080204Abstract: Disclosed are various techniques for deploying multiple processing resources, operating in parallel, to compile electronic designs. The disclosed methods identify "compilation tasks" that can be performed in isolation from the remainder of a large "compilation project." When one of these stand alone compilation tasks is identified, it can be temporarily segregated and performed by one or more processors which are not working on other tasks. Simultaneously, the remainder of the project compiles under one or more other processors. One class of severable compilation projects includes those projects that contain multiple full compilation tasks, each of which involves compiling a single design from start to finish. Another class of divisible compilation projects includes those projects in which the logical hierarchy of an electronic design provides the boundaries between isolated compilation tasks.Type: GrantFiled: October 27, 1997Date of Patent: June 27, 2000Assignee: Altera CorporationInventor: David Wolk Mendel
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Patent number: 5691653Abstract: The number of programmable control elements required in a programmable AND array for use in a product term based programmable logic array device is reduced by generally feeding only the true or complement of each input logic signal into the AND array on an associated main word line conductor. Auxiliary word line conductors are provided for those input logic signals that are required in both true and complement form. The number of auxiliary word line conductors is less than the number of main word line conductors, which can reduce the required number of programmable control elements as compared to a conventional programmable AND array in which both the true and complement of all input logic signals are fed into the array.Type: GrantFiled: January 16, 1996Date of Patent: November 25, 1997Assignee: Altera CorporationInventor: David Wolk Mendel
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Patent number: 5670895Abstract: Logic signal routability in programmable logic array integrated circuit devices is improved by selecting the possible interconnections between various resources on the device so that various constraints or goals are satisfied. Improving routability in this way tends to reduce instances in which desired interconnections are blocked by other connections that have already been made.Type: GrantFiled: October 19, 1995Date of Patent: September 23, 1997Assignee: Altera CorporationInventors: Peter J. Kazarian, Bruce B. Pedersen, Francis B. Heile, David Wolk Mendel