Patents by Inventor David X. Zhang
David X. Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160248695Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Gregory Marlan, Kenneth Yeager, Mahdi Seddighnezhad, David X. Zhang
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Patent number: 9271267Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.Type: GrantFiled: May 22, 2012Date of Patent: February 23, 2016Assignee: Silicon Graphics International Corp.Inventors: Gregory Marlan, Kenneth Yeager, Mahdi Seddighnezhad, David X. Zhang
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Publication number: 20120272002Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.Type: ApplicationFiled: May 22, 2012Publication date: October 25, 2012Inventors: Gregory Marlan, Kenneth Yeager, Mahdi Seddighnezhad, David X. Zhang
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Patent number: 8185703Abstract: In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.Type: GrantFiled: July 31, 2003Date of Patent: May 22, 2012Assignee: Silicon Graphics International Corp.Inventors: Gregory Marlan, Kenneth Yeager, Mahdi Seddighnezhad, David X. Zhang
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Patent number: 7406587Abstract: A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.Type: GrantFiled: July 31, 2002Date of Patent: July 29, 2008Assignee: Silicon Graphics, Inc.Inventors: David X. Zhang, Kenneth C. Yeager
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Patent number: 7007205Abstract: An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response to various triggering events. The information captured by the trace recorder (20) may subsequently be provided to external test equipment in order to analyze the operation of the central processing unit (12) for failure correction.Type: GrantFiled: February 15, 2001Date of Patent: February 28, 2006Assignee: Silicon Graphics, Inc.Inventors: Kenneth C. Yeager, Steven T. Peltier, David X. Zhang
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Patent number: 6986001Abstract: A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N memory blocks. The N memory blocks are allocated as M super-ways of N/M memory blocks where N is greater than M. An index identifies the set of N memory blocks. A super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements for each super-way where the super-ways are ordered from the MRU to the LRU. Storage for the state bits is associated with each index entry where the state bits include code bits associated with a memory block to be replaced within a LRU super-way. LRU logic is coupled to the super-way hit/replacement tracking state machine to select an LRU super-way as a function of the super-way hit and replacement history.Type: GrantFiled: October 21, 2002Date of Patent: January 10, 2006Assignee: Silicon Graphics, Inc.Inventor: David X. Zhang
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Patent number: 6904501Abstract: A cache memory includes a plurality of data memory blocks and a code memory block. Each data memory block has a plurality of storage locations and has a particular storage location identified by a same index value. The code memory block has a plurality of code values with a particular code value being associated with the same index value. The particular code value is operable to identify which ones of the particular storage locations associated with the same index value are locked to prevent alteration of contents therein. The particular code value is also operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the same index value.Type: GrantFiled: June 17, 2002Date of Patent: June 7, 2005Assignee: Silicon Graphics, Inc.Inventors: David X. Zhang, Kenneth C. Yeager
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Patent number: 6738885Abstract: An information capturing device (10) includes a controller (12) and a memory (14). The controller (12) partitions a memory space of the memory (14) into a plurality of memory blocks (20). The controller (12) controls the storage of received information into a first set (22) of the plurality of memory blocks (20). The controller (12) continues to store received information only in the first set (22) of the plurality of memory blocks (20) through reuse and recycle until a first triggering event occurs. In response to the first triggering event, the controller (12) halts the storage of received information in the first set (22) of the plurality of memory blocks (20) and begins storing received information in a second set (24) of the plurality of memory blocks (20). When the second set (24) of the plurality of memory blocks (24) has reached its storage capacity, the controller (12) begins storing received information in a third set (26) of the plurality of memory blocks (20).Type: GrantFiled: February 15, 2001Date of Patent: May 18, 2004Assignee: Silicon Graphics, Inc.Inventors: David X. Zhang, Kenneth C. Yeager, Steven T. Peltier
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Publication number: 20040078526Abstract: A system for approximating a least recently used (LRU) algorithm for memory replacement in a cache memory. In one system example, the cache memory comprises memory blocks allocated into sets of N memory blocks. The N memory blocks are allocated as M super-ways of N/M memory blocks where N is greater than M. An index identifies the set of N memory blocks. A super-way hit/replacement tracking state machine tracks hits and replacements to each super-way and maintains state corresponding to an order of hits and replacements for each super-way where the super-ways are ordered from the MRU to the LRU. Storage for the state bits is associated with each index entry where the state bits include code bits associated with a memory block to be replaced within a LRU super-way. LRU logic is coupled to the super-way hit/replacement tracking state machine to select an LRU super-way as a function of the super-way hit and replacement history.Type: ApplicationFiled: October 21, 2002Publication date: April 22, 2004Applicant: Silicon Graphics, Inc.Inventor: David X. Zhang
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Patent number: 6634011Abstract: An integrated circuit (10) includes a central processing unit (12), an instruction cache (14), a data cache, (16), and a trace recorder. The central processing unit (12) interacts with the instruction cache (14) and the data cache (16) in order to execute instructions. Profile information passed between the central processing unit (12), the instruction cache (14), and the data cache (16) not normally available for external analysis may be captured by the trace recorder (20) in response to various execution points in a program being executed by the central processing unit (12). The profile information captured by the trace recorder (20) may subsequently be provided to external analysis equipment in order to analyze the operation of the central processing unit (12) for study of program execution.Type: GrantFiled: February 15, 2001Date of Patent: October 14, 2003Assignee: Silicon Graphics, Inc.Inventors: Steven T. Peltier, David X. Zhang, Kenneth C. Yeager