Abstract: Techniques pertaining to battery protection circuits are disclosed. According to one embodiment of the present invention, the battery protection circuit includes a power button, a power detection circuit, a first switch coupled between the power button and the power detection circuit, the power detection circuit configured to output a power-off signal when either the first switch or the power button is in a switch-off state, a low-voltage detection circuit coupled with a battery and configured to detect whether a voltage of the battery is lower than a low-voltage detection threshold or not, and switch off the first switch to cut off an electric leakage path of the battery when the voltage of the battery is determined to be lower than the low-voltage detection threshold, and a power management circuit coupled with the power detection circuit and configured to cut off an electric discharge path of the battery to prohibit the battery from discharging when receiving the power-off signal.

Abstract: Techniques for a personalized Bluetooth headset and a voice interaction control method thereof are described. According to one aspect of the present invention, the Bluetooth headset is configured to create and maintain a voice-based table. Each item in the table includes a phone number paired with a set of audio data (e.g., a voice or a predefined audio), where the audio data is created by a user. When a paired mobile device receives a call, the table is searched per the caller number. A corresponding audio is played back first when an item is located in the table. As such a user of the Bluetooth headset knows who is calling and determines whether the call shall be answered or not.

Abstract: Techniques pertaining to battery protection circuits are disclosed. According to one embodiment of the present invention, the battery protection circuit includes a power button, a power detection circuit, a first switch coupled between the power button and the power detection circuit, the power detection circuit configured to output a power-off signal when either the first switch or the power button is in a switch-off state, a low-voltage detection circuit coupled with a battery and configured to detect whether a voltage of the battery is lower than a low-voltage detection threshold or not, and switch off the first switch to cut off an electric leakage path of the battery when the voltage of the battery is determined to be lower than the low-voltage detection threshold, and a power management circuit coupled with the power detection circuit and configured to cut off an electric discharge path of the battery to prohibit the battery from discharging when receiving the power-off signal.

Abstract: A video imaging system includes a digital image sensor for performing image capture operations and a digital image processor for performing image processing operations. The digital image sensor includes a sensor array outputting digital pixel data, an image buffer for storing the pixel data, a first processor and a first interface circuit for transferring the pixel data onto a pixel bus. The digital image processor includes a second interface circuit coupled to receive the pixel data from the pixel bus, a frame buffer coupled to store the pixel data, an image processing pipeline for processing the pixel data stored in the frame buffer into video data, and a second processor. The digital image sensor and the digital image processor transfer control information over a control interface bus and the digital image sensor performs the image capture operations independent of the image processing operations performed by the digital image processor.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: A system-on-chip imaging system includes an image sensor of a two-dimensional array of pixel elements providing pixel data representing an image of a scene, a data memory for storing pixel codewords whereby at least some of the pixel codewords are indicative of the pixel data, a programmable lookup table for providing LUT codewords as output data, and a processing unit for receiving LUT codewords from the lookup table and generating output image data. In operation, a first pixel codeword stored in the data memory is used to index the lookup table for causing the lookup table to provide a respective LUT codeword to the processing unit. The processing unit operates to perform one or more image processing functions in response to the LUT codeword. The lookup table can be programmed to perform a variety of image processing functions, including defective pixel correction, CDS subtraction, privacy masking and dark signal subtraction.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Abstract: An architecture for a digital pixel sensor is disclosed in which the dynamic range of the sensor is increased by taking samples of a subject to be recorded, where each sample is taken over an interval of a different duration than the other samples. In the preferred embodiment of the invention, an array of pixel elements is fabricated in an integrated circuit. Each of the pixel elements outputs a digital signal and comprises a photodetector and an analog to digital converter. The photodetector is integrated with the analog to digital converter. An array of threshold memory cells, each corresponding to one of the pixel elements, is also provided. An array of time memory cells, each corresponding to one of the pixel elements, establishes a different sampling time for each of the pixel elements for each of multiple samples. An array of memory elements, each coupled to one of the pixel elements, is also provided. The memory elements are also fabricated in the integrated circuit.

Abstract: An image sensor includes a sensor array including a two-dimensional array of pixel elements. The array of pixel elements includes a first group of photodetectors having a first sensitivity level and a second group of photodetectors having a second sensitivity level. The sensor array outputs digital signals as pixel data representing an image of a scene. In operation, the first group of photodetectors generates the output signals after a first exposure time and the second group of photodetectors generates the output signals after a second exposure time, where the first exposure time and the second exposure time are within a snapshot of the scene and the first exposure time is different than the second exposure time. When thus operated, the image sensor of the present invention provides improved color reproduction capability and improved signal to noise ratio, especially for the less sensitive photosensitive elements.

Abstract: An improved technique for updating a memory in digital pixel sensors in which a memory update may be directed to only some of the locations or cells in the memory is disclosed. According to one embodiment, a multiplex scheme is employed, in which a threshold memory identifies the locations within a row of memory that are to be updated. Data are first read out of a row of memory to be updated. The data are copied to a first buffer or other short term storage area within the digital pixel sensor. New data from the sensor portion of the digital pixel sensor to be written to the memory are stored in a second buffer. The contents of the threshold memory are then applied to a select input of a multiplexer, where the contents of the first and second buffers comprise first and second data inputs to the multiplexer. Thus, the output of the multiplexer comprises an updated row of memory in which only those locations that are to be updated have been changed.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: A digital photoimaging device is presented. The digital photoimaging device includes a photosensor array having supporting circuitry formed on a second substrate produced, for example, with CMOS process technology and photosensors formed on a first substrate. The first substrate is processed separately from the second substrate so that the photosensors formed on the first substrate can be optimized while also optimizing the circuitry formed on the second substrate. The first substrate is then placed into electrical contact with the second substrate so that signals from the photosensors on the first substrate arc received by the supporting circuitry on the second substrate. In one embodiment, the supporting circuitry includes an array of support circuits each including an analog-to-digital converter.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: An image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory is disclosed. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.

Abstract: A circuit includes an input terminal coupled to receive an analog input signal, a multiple number of sample-and-hold circuits and a multiple number of analog-to-digital (A/D) converters. The input terminal of each of the sample-and-hold circuits is coupled to receive the analog input signal. Each of the A/D converters has an input terminal and an output terminal, where the input terminal is coupled to an output terminal of a corresponding one of the sample-and-hold circuits. In operation, the sample-and-hold circuits sample the analog input signal sequentially and store a multiple number of analog samples at each of the sample-and-hold circuits. The A/D converters convert the analog samples in parallel to generate digital values at the output terminals of each of the A/D converters representative of each of the analog samples. In one embodiment, the A/D converters are implemented based on a multi-channel bit-serial (MCBS) analog-to-digital conversion scheme.

Abstract: An image sensor, including a substrate having formed thereon by a CMOS process a digital sensor array having a plurality of digital pixel sensors which output analog signals corresponding to a desired image. The digital sensor array further includes supporting circuitry for converting the analog signals produced by the digital pixel sensors to digital signals corresponding to the desired image. Filter circuitry, for converting the digital signals to digital values representative of the light intensity impinging upon the plurality of digital pixel sensors, is also formed on the substrate using CMOS fabrication processes. Memory devices, including a data memory, a threshold memory, and a time index memory are formed on the substrate using CMOS fabrication techniques. A clock circuit is also formed on the substrate using CMOS fabrication processes. Programmable logic structures are formed on the substrate using CMOS fabrication processes.

Abstract: A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

Abstract: A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout.

Abstract: A circuit includes an input terminal coupled to receive an analog input signal, a multiple number of sample-and-hold circuits and a multiple number of analog-to-digital (A/D) converters. The input terminal of each of the sample-and-hold circuits is coupled to receive the analog input signal. Each of the A/D converters has an input terminal and an output terminal, where the input terminal is coupled to an output terminal of a corresponding one of the sample-and-hold circuits. In operation, the sample-and-hold circuits sample the analog input signal sequentially and store a multiple number of analog samples at each of the sample-and-hold circuits. The A/D converters convert the analog samples in parallel to generate digital values at the output terminals of each of the A/D converters representative of each of the analog samples. In one embodiment, the A/D converters are implemented based on a multi-channel bit-serial (MCBS) analog-to-digital conversion scheme.