Abstract: An apparatus and method for micro-exercise apply piezoelectric stress to cells of a bone mass by inducing voltages in the bone mass. Application of dynamic, electromagnetic fields passing through the conductive bone mass induce currents and voltages locally in and around cells or groups of cells. The cells respond to the combination of mechanical stress and strain by building themselves up as they would if they had been subjected to the stress and strain of conventional exercise. Thus, micro-exercise at a cellular level of the bone mass can be stimulated as if the stress and strain had been applied to the entire bone structure of which the smaller cellular portions are constituent parts. In combination with casts or splints, the sources of electromagnetic flux may be embedded in the frame or solid structure, the protective padding added for comfort, or both.

Abstract: An apparatus and method for micro-exercise apply piezoelectric stress to cells of a bone mass by inducing voltages in the bone mass. Application of dynamic, electromagnetic fields passing through the conductive bone mass induce currents and voltages locally in and around cells or groups of cells. The cells respond to the combination of mechanical stress and strain by building themselves up as they would if they had been subjected to the stress and strain of conventional exercise. Thus, micro-exercise at a cellular level of the bone mass can be stimulated as if the stress and strain had been applied to the entire bone structure of which the smaller cellular portions are constituent parts. In combination with casts or splints, the sources of electromagnetic flux may be embedded in the frame or solid structure, the protective padding added for comfort, or both.

Abstract: Techniques for simultaneously and efficiently eliminating echo and noise mixed in voice are disclosed. According to one aspect of the present invention, an adaptive filter system for eliminating noises and echo mixed in voice signal comprises a first signal adaptive filter, a first subtractor, a second adaptive filter and a second subtractor. The first signal adaptive filter estimates the noise mixed in the voice signal according to a reference noise. The first subtractor subtracts the noise estimated by the first adaptive filter from the voice signal to obtain a voice signal without the mixed noise. The second adaptive filter estimates the echo mixed in the voice signal according to a remote voice signal. The second subtractor subtracts the echo estimated by the second adaptive filter from the voice signal without mixed noise to obtain a clean voice signal.

Abstract: Techniques for storing and reading data on/from a hard disk are disclosed. According to one aspect of the present invention, a hard disk is provided with a parameter storage block for storing a number of parameters. One of the parameters is a last physical address the hard disk was accessed. The last physical address is used as a reference to read data segments onto the hard disk. Each of the data segments is a compressed version of a portion of data to be stored in the hard disk. A portion of the data is allocated in accordance with a predefined time period. Accordingly, the compressed data portion also includes a header including information about the compressed data portion. The information includes at least a compression scheme used as well as the time about the data portion. Based on how the data is stored, a corresponding reading method is also provided.

Abstract: A video imaging system includes a digital image sensor for performing image capture operations and a digital image processor for performing image processing operations. The digital image sensor includes a sensor array outputting digital pixel data, an image buffer for storing the pixel data, a first processor and a first interface circuit for transferring the pixel data onto a pixel bus. The digital image processor includes a second interface circuit coupled to receive the pixel data from the pixel bus, a frame buffer coupled to store the pixel data, an image processing pipeline for processing the pixel data stored in the frame buffer into video data, and a second processor. The digital image sensor and the digital image processor transfer control information over a control interface bus and the digital image sensor performs the image capture operations independent of the image processing operations performed by the digital image processor.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: A system-on-chip imaging system includes an image sensor of a two-dimensional array of pixel elements providing pixel data representing an image of a scene, a data memory for storing pixel codewords whereby at least some of the pixel codewords are indicative of the pixel data, a programmable lookup table for providing LUT codewords as output data, and a processing unit for receiving LUT codewords from the lookup table and generating output image data. In operation, a first pixel codeword stored in the data memory is used to index the lookup table for causing the lookup table to provide a respective LUT codeword to the processing unit. The processing unit operates to perform one or more image processing functions in response to the LUT codeword. The lookup table can be programmed to perform a variety of image processing functions, including defective pixel correction, CDS subtraction, privacy masking and dark signal subtraction.

Abstract: Techniques pertaining to a circuit architecture capable of controlling a current source to a predefined precision are disclosed. According to one aspect of the present invention, an automatic trimming circuit is proposed to automatically trim a current generated from a current generator or circuit in accordance with a reference current. The automatic trimming circuit includes a comparator, an ADC and a register. The comparator that may be implemented as a subtractor finds a difference between a generated current and a reference current. The difference is then digitized to an n-bit precision. A digital representation of the difference is then kept in a register and used subsequently correct or modify the generated current to produce a precisely controlled current.

Abstract: Techniques for transmitting data between devices based on two-dimensional symbols are disclosed, where the devices are generally not equipped with the traditional networking capabilities, or at least these traditional networking capabilities are not used for the data communication. According to one aspect of the techniques, two devices communicate with each other by displaying one or more two-dimensional symbols. Data is encoded into one or more symbols that are displayed on one of the devices. Images of the symbols are taken by another one of the devices to receive the data. These images are sequentially processed and decoded so that the data is now received. To accommodate various environments, the system is configured to adjust parameters pertaining to the symbols to achieve an optimum transmission rate.

Abstract: A series of improved processes and methods to manufacture solder bumps on the wafer which shrink the space among solder bumps and reduce the cost of manufacturing. A design method and a relevant manufacturing process are introduced to form an organic material or metal material layer, which is called a Bump-Reflow-Control Layer. The pad patterns can be defined by this method. A mechanical part is designed with a hermetic cover to improve the photoresist process. The series of photolithography process including the designing method of related photolithography mask is introduced to achieve the high quality and thick photoresist.

Abstract: Techniques for transmitting data between devices based on two-dimensional symbols are disclosed, where the devices are generally not equipped with the traditional networking capabilities, or at least these traditional networking capabilities are not used for the data communication. According to one aspect of the techniques, two devices communicate with each other by displaying one or more two-dimensional symbols. Data is encoded into one or more symbols that are displayed on one of the devices. Images of the symbols are taken by another one of the devices to receive the data. These images are sequentially processed and decoded so that the data is now received. To accommodate various environments, the system is configured to adjust parameters pertaining to the symbols to achieve an optimum transmission rate.

Abstract: A method for the fine-pitch stencil mask design for stencil printing bumping technology for eutectic Sn/Pb and lead-free solder material is described. In the method, a reflowing enhancement layer is introduced to improve the solder quality and reduce the pitch of solder bumps. The method of forming the layer is described as well as the forming method of matching under-bump metallurgy layer. The method of stencil mask design can match various sizes and pitch of the solder bumps. The designed mask is fixed on the stencil printer to deposit the solder materials with the required patterns. This method can increase the solder paste volume to increase the height of solder bumps after the reflowing process.

Abstract: Techniques for transmitting image data via the DMAC are disclosed. According to one aspect of the techniques, a DMA controller for an image data transmission system comprises a bus interface for receiving/transmitting data from/to a system bus; a request processing unit for processing a DMA request from a peripheral equipment and making a DMA response for the DMA request; a data, address, control register unit for storing data, address and control information from the bus interface; a macro block information register unit for storing macro block information of a macro block data which is pending for data transmission; and a control logic unit calculating continuous address ranges of the pending macro block data in a memory according to the macro block information so that corresponding continuous address data of the macro block is transmitted according to the continuous address ranges, respectively.

Abstract: An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Abstract: An architecture for a digital pixel sensor is disclosed in which the dynamic range of the sensor is increased by taking samples of a subject to be recorded, where each sample is taken over an interval of a different duration than the other samples. In the preferred embodiment of the invention, an array of pixel elements is fabricated in an integrated circuit. Each of the pixel elements outputs a digital signal and comprises a photodetector and an analog to digital converter. The photodetector is integrated with the analog to digital converter. An array of threshold memory cells, each corresponding to one of the pixel elements, is also provided. An array of time memory cells, each corresponding to one of the pixel elements, establishes a different sampling time for each of the pixel elements for each of multiple samples. An array of memory elements, each coupled to one of the pixel elements, is also provided. The memory elements are also fabricated in the integrated circuit.

Abstract: An image sensor includes a sensor array including a two-dimensional array of pixel elements. The array of pixel elements includes a first group of photodetectors having a first sensitivity level and a second group of photodetectors having a second sensitivity level. The sensor array outputs digital signals as pixel data representing an image of a scene. In operation, the first group of photodetectors generates the output signals after a first exposure time and the second group of photodetectors generates the output signals after a second exposure time, where the first exposure time and the second exposure time are within a snapshot of the scene and the first exposure time is different than the second exposure time. When thus operated, the image sensor of the present invention provides improved color reproduction capability and improved signal to noise ratio, especially for the less sensitive photosensitive elements.