Abstract: A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.

Abstract: An apparatus connects a data processing system (10) with an analog telephone line and/or an ISDN line. The apparatus modulates and demodulates data from the data processing system (10) to either of the two different telephone protocols without adding unnecessary expense or noise to the system.

Abstract: A digital signal processor (10) for implementing a gain instruction. The gain instruction, when decoded, controls a multiplexer (43) to select a gain control index signal. The value of the chosen gain control index signal is added to a program control register (48) to produce a program address. The program address is used to choose one of four gain values specified by the gain instruction. The gain value is multiplied by a value accessed through an address indirect register, also specified by the instruction, and the result is stored in an accumulator.

Abstract: A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Abstract: Data converter (10, 50, 150, 200) and method (250, 300) operate at variable sampling rates. Input gain stage (12) adjusts input bit stream (18) at an input bit rate (20) to produce gain adjusted bit stream (22). Integrator (14) and comb filter (16) operate on the gain adjusted bit stream (22) to produce a filtered bit stream (28) at an output bit rate (24). The gain of the integrator (14) and comb filter (16) pair varies with the sampling rates implemented. An input gain value of the input gain stage (12) adjusts to compensate for the gain of the integrator (14) and comb filter (16) pair to produce the filtered bit stream (28) within a predetermined dynamic range. DC offset stage (52) and output gain stage (54) provide further adjustment to the filtered bit stream (28). Data converters (10, 50) and method (250) convert data from a higher frequency bit rate to a lower frequency bit rate. Data converters (150, 200) and method (300) convert data from a lower frequency bit rate to a higher frequency bit rate.

Abstract: A method and apparatus for a multiply accumulate circuit (10) having a programmable saturation value is accomplished by providing saturation logic (20) that receives a saturation range signal (32) from a Digital Signal Processor (DSP) programmer. The saturation range signal (32) is then converted to a selected saturation value (34) and provided as an input to the saturation logic (20). The saturation logic (20) utilizes the selected saturation value (34) to establish an intermediate saturation value (30). For each intermediate resultant generated by the multiply and accumulate circuit (10), the intermediate resultant is compared with the intermediate saturation value (30). When the intermediate resultant compares unfavorably to the intermediate saturation value (30), a saturation default value (42) is supplied to the accumulator register. Additionally, the final accumulate result is compared against a final saturation value, and, if unfavorable, a saturation value is provided as the final result.

Abstract: A D/A converter (10) converts a digitized analog signal (32) to an analog signal (50). The D/A converter (10) includes first filtering stage (12), second filtering stage (14), and reduced-bit D/A converter (16). The first filtering stage (12) operates at a first sampling rate (25), interpolates the digitized analog signal (32) from an initial sampling rate to a first sampling rate (25), performs an anti-alias filter, and performs a first comb filtering function. The second filtering stage (14) operates at a second sampling rate (46), interpolates the digitized analog signal (32) to the second sampling rate (46), performs a second comb filtering function, and performs a noise shaper filter to produce a reduced-bit second sampling rate signal (48). The reduced-bit D/A converter (16) converts the second sampling rate signal (48) to an analog signal (50).

Abstract: A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Abstract: An ADPCM transcoder (60) includes an integral tone generator (65) which inserts a linear tone signal, such as a conventional DTMF tone signal, into either the transmit or receive data stream, or both. A digital PCM input signal is first converted to a first linear signal. If tone generation is enabled for transmission, then the linear tone signal is substituted for or added to the first linear signal and provided to an ADPCM encoder (63), which provides an ADPCM output signal in response. An ADPCM decoder (66) receives an ADPCM input signal and provides a second linear input signal in response. If tone generation is enabled for reception, then the linear tone signal is substituted for or added to the second linear input signal, and converted to a digital PCM output signal. The ADPCM transcoder (60) may also be integrated with other components of a signal processing system.

Abstract: A signal processor such as an ADPCM decoder (28b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, ADPCM decoder (28b) processes the input signal to provide a linear reconstructed signal s.sub.r (k). When enabled, a noise detector (50) samples the reconstructed signal s.sub.r (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of the reconstructed signal s.sub.r (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. This calculation prevents the need for time-consuming division operation which is difficult for high-performance digital signal processors (70).

Abstract: An integral digital receive gain (44) for a G.721 or G.726 ADPCM decoder (28a) or the like in an application such as a CT-2 handset (20) allows digital volume control without the need for external components. The digital receive gain (44) receives a reconstructed signal s.sub.r (k) and a variable gain factor. The integral digital receive gain (44) multiplies the reconstructed signal by the gain factor and provides the result as an input to an output PCM format conversion (45). The digital receive gain (44) also disables a synchronous coding adjustment (46) if a gain setting other than unity gain is detected.