Patents by Inventor David Yepejian Lepejian

David Yepejian Lepejian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for using wafer navigation to reduce testing times of integrated circuit wafers
    Patent number: 6154714
    Abstract: A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: November 28, 2000
    Assignee: Heuristic Physics Laboratories
    Inventor: David Yepejian Lepejian