Patents by Inventor David Yiu-Man Lau
David Yiu-Man Lau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10496461Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.Type: GrantFiled: June 15, 2011Date of Patent: December 3, 2019Assignee: ARM Finance Overseas LimitedInventor: David Yiu-Man Lau
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Patent number: 10318290Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: GrantFiled: May 24, 2017Date of Patent: June 11, 2019Assignee: ARM Finance Overseas LimitedInventor: David Yiu-Man Lau
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Publication number: 20170255464Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: ApplicationFiled: May 24, 2017Publication date: September 7, 2017Inventor: David Yiu-Man Lau
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Patent number: 9690579Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: GrantFiled: December 29, 2014Date of Patent: June 27, 2017Assignee: ARM Finance Overseas LimitedInventor: David Yiu-Man Lau
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Publication number: 20150121044Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: ApplicationFiled: December 29, 2014Publication date: April 30, 2015Inventor: David Yiu-Man Lau
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Patent number: 8924454Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: GrantFiled: January 25, 2012Date of Patent: December 30, 2014Assignee: Arm Finance Overseas LimitedInventor: David Yiu-Man Lau
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Publication number: 20130191426Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.Type: ApplicationFiled: January 25, 2012Publication date: July 25, 2013Applicant: MIPS TECHNOLOGIES, INC.Inventor: David Yiu-Man Lau
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Patent number: 8392644Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.Type: GrantFiled: July 30, 2010Date of Patent: March 5, 2013Assignee: MIPS Technologies, Inc.Inventors: Erik K. Norden, David Yiu-Man Lau, James H. Robinson
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Publication number: 20120324164Abstract: A method includes storing defined memory address segments and defined memory address segment attributes for a processor. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes.Type: ApplicationFiled: June 15, 2011Publication date: December 20, 2012Applicant: MIPS TECHNOLOGIES, INC.Inventor: David Yiu-Man Lau
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Publication number: 20120323552Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.Type: ApplicationFiled: June 15, 2011Publication date: December 20, 2012Applicant: MIPS TECHNOLOGIES, INC.Inventor: David Yiu-Man Lau
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Publication number: 20120030392Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Applicant: MIPS Technologies, Inc.Inventors: Erik K. Norden, David Yiu-Man Lau, James H. Robinson
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Publication number: 20100312991Abstract: A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions, including instructions with encoded arguments determined by statistical analysis and instructions that have the effect of combinations of instructions.Type: ApplicationFiled: March 26, 2010Publication date: December 9, 2010Applicant: MIPS Technologies, Inc.Inventors: Erik K. NORDEN, James Hippisley Robinson, David Yiu-Man Lau