Abstract: A method for polishing front and back surfaces of a semiconductor wafer includes the step of providing a polishing apparatus having a wafer carrier generally disposed between a first polishing pad and a second polishing pad. The first pad has a hardness significantly greater than a hardness of the second pad. The wafer is placed in the wafer carrier so that the front surface faces the first pad and so that the back surface faces the second pad. A polishing slurry is applied to at least one of the pads and the carrier, first pad and second pad are rotated. The front surface is brought into contact with the first pad and the back surface is brought into contact with the second pad for polishing the front and back surfaces of the wafer whereby less wafer material is removed from the back surface engaged by the second pad and the back surface has less gloss than the front surface after polishing so that the front surface and back surface are visually distinguishable.

Abstract: An integrated overvoltage and overcurrent circuit protection device for use in telecommunication circuits. The integrated circuit protection device combines a overcurrent device such as a fuse and a overvoltage protection device such as a thyristor to respectively protect against overcurrent conditions and transient overvoltages. Integration of multiple devices in a common package ensures proper coordination and matching of the components, reduces the final product cost and reduces the physical space required on a telecommunications circuit for overvoltage and overcurrent circuit protection.

Abstract: A method for repairing a wafer carrier after plural processing operations during which the carrier holds a plurality of semiconductor wafers in a processing apparatus which removes wafer material by at least one of abrading and chemical reaction. The wafer carrier has holes for receiving respective ones of the wafers and removable annular inserts for each hole. Each insert is receivable in a respective one of the holes for engaging a peripheral edge of one of the wafers. The thickness of the insert is reduced during the successive processing operations. The method includes removing at least one of the inserts from the wafer carrier and installing at least one new insert in the wafer carrier having a thickness substantially greater than a minimum thickness to extend the useful life of the wafer carrier and to improve the flatness and parallelism of surfaces of wafers processed using the wafer carrier.

Abstract: A method of manufacturing a semiconductor wafer includes providing an ingot of semiconductor material, slicing the wafer from the ingot, and processing the wafer to increase parallelism of the front surface and the back surface. A final polishing operation on at least the front surface is performed by positioning the wafer between a first pad and a second pad and obtaining motion of the front and back surfaces of the wafer relative to the first and second pads to maintain parallelism of the front and back surfaces and to produce a finish on at least the front surface of the wafer so that the front surface is prepared for integrated circuit fabrication. In another aspect, the wafer is rinsed by a rinsing fluid to increase hydrodynamic lubrication. Other methods are directed to conditioning the polishing pad and to handling wafers after polishing. An apparatus for polishing wafers is also included.

Abstract: A semiconductor wafer manufacturing process is disclosed wherein extremely flat, double side polished semiconductor wafers having enhanced gettering characteristics on the back surface are produced. The process includes creating an enhanced gettering layer on the back surface of a double side polished semiconductor wafer. A protective layer is subsequently grown on the enhanced gettering layer and the wafer is subsequently subjected to a second double side polishing operation. Finally, the protective layer is removed and the front surface final polished to produce an extremely flat semiconductor wafer having enhanced gettering characteristics on the back surface.

Abstract: A multi-step polishing process for producing dopant-striation-free semiconductor wafers. The process includes polishing a surface of the wafer using a sodium stabilized colloidal silica slurry, an amine accelerant, and an alkaline etchant, polishing the surface of the wafer using a sodium stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants, and polishing the surface of the wafer using an ammonia stabilized colloidal silica slurry and an alkaline etchant which is substantially free of amine accelerants.

Abstract: A process for joining together a first polishing pad with a second polishing pad to form a larger pad for a machine that performs chemical-mechanical polishing of silicon wafers. The process includes laying a first polishing pad on a surface and laying a second pad on the surface so that a portion of the second pad overlies a portion of the first pad, creating an overlap region. The first and second pads in the overlap region are cut through to form a first cut edge on the first pad and a second cut edge on the second pad, the first and second cut edges having shapes which are complementary. The first and second cut edges are brought into engagement, and the first pad is joined to the second pad at the first and second cut edges.

Abstract: A method of conditioning a polishing pad for use with a polishing machine. The method includes installing the polishing pad to be conditioned on the polishing machine's platen and applying a conditioning load force to the pad. In addition, the method includes supplying a slurry to the pad at a conditioning flow rate. The conditioning load force is greater than a polishing load force applied during a conventional wafer polishing cycle to compress the pad and the conditioning flow rate is greater than a polishing flow rate at which the slurry is supplied during the wafer polishing cycle to load the pad's pores with abrasive material. The method also includes the step of operating the polishing machine for a conditioning cycle while applying the conditioning load force and supplying the slurry at the conditioning flow rate. In this manner, the polishing pad is conditioned for use with the polishing machine for subsequently polishing the semiconductor wafers with the conditioned pad.

Abstract: Batch and continuous-flow cell-free methods for synthesizing protein wherein translation is coupled with replication of recombinant mRNA by an RNA-directed RNA polyerase, such as Q.beta. replicase. Transcription of a DNA template to produce the recombinant mRNA can be coupled additionally with coupled transcription-replication-translation methods, both batch and continuous. The invention also includes kits of reagents for synthesizing user-selected proteins according to methods of this invention.