Patents by Inventor David Zubia
David Zubia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10931282Abstract: A personal laboratory includes a self-contained, miniaturized, portable kit that provides for design, testing, and automated assembling, dissembling, and reassembling of a physical system (rather than a simulation) with flexibility as to the variety of configurations of components that may be designed and assembled, and easy integration of complex components. The personal laboratory includes a reconfigurable system, the reconfigurable system includes a plurality of functional components, and a plurality of connectors configured for operatively connect respective functional components to other functional components; a stimulus generator configured to apply a stimulus to the reconfigurable system; and a measurement system configured to measure a response to the applied stimulus generated by the reconfigurable system. In the context of electronic circuits, the reconfigurable system is a reconfigurable circuit, the functional components are circuit elements and the connectors are electrical connectors.Type: GrantFiled: June 7, 2017Date of Patent: February 23, 2021Assignee: Board of Regents, The University of Texas SystemInventors: David Zubia, Sergio F. Almeida Loya
-
Patent number: 10392243Abstract: A MEMS apparatus with dynamic displacement control includes a MEMS parallel plate capacitor integrated with one or more memristors in a series configuration wherein a displacement is observable as a function of memristance, such that an upper electrode position is capable of being interpreted in a form of a resistance rather than a capacitance. The current is limited by said MEMS parallel plate capacitor restricting a change in the resistance of the memristor(s). The memristor(s) can be employed in some embodiments a sensor element to improve a MEMS operation range.Type: GrantFiled: October 1, 2015Date of Patent: August 27, 2019Assignees: Board of Regents, The University of Texas System, National Technology & Engineering Solutions of Sandia, LLCInventors: Sergio Fabian Almeida Loya, David Zubia, Ernest J. Garcia, Jose Mireles, Jr.
-
Publication number: 20170363678Abstract: A personal laboratory includes a self-contained, miniaturized, portable kit that provides for design, testing, and automated assembling, dissembling, and reassembling of a physical system (rather than a simulation) with flexibility as to the variety of configurations of components that may be designed and assembled, and easy integration of complex components. The personal laboratory includes a reconfigurable system, the reconfigurable system includes a plurality of functional components, and a plurality of connectors configured for operatively connect respective functional components to other functional components; a stimulus generator configured to apply a stimulus to the reconfigurable system; and a measurement system configured to measure a response to the applied stimulus generated by the reconfigurable system. In the context of electronic circuits, the reconfigurable system is a reconfigurable circuit, the functional components are circuit elements and the connectors are electrical connectors.Type: ApplicationFiled: June 7, 2017Publication date: December 21, 2017Inventors: David Zubia, Sergio F. Almeida Loya
-
Publication number: 20170297908Abstract: A MEMS apparatus with dynamic displacement control includes a MEMS parallel plate capacitor integrated with one or more memristors in a series configuration wherein a displacement is observable as a function of memristance, such that an upper electrode position is capable of being interpreted in a form of a resistance rather than a capacitance. The current is limited by said MEMS parallel plate capacitor restricting a change in the resistance of the memristor(s). The memristor(s) can be employed in some embodiments a sensor element to improve a MEMS operation range.Type: ApplicationFiled: October 1, 2015Publication date: October 19, 2017Inventors: Sergio Fabian Almeida Loya, David Zubia, Ernest J. Garcia, Jose Mireles, Jr.
-
Patent number: 9685580Abstract: A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.Type: GrantFiled: September 14, 2016Date of Patent: June 20, 2017Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Jose Luis Cruz-Campa, Xiaowang Zhou, David Zubia
-
Publication number: 20170005222Abstract: A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Jose Luis Cruz-Campa, Xiaowang Zhou, David Zubia
-
Patent number: 9472702Abstract: A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.Type: GrantFiled: November 19, 2012Date of Patent: October 18, 2016Assignees: Sandia Corporation, The Board of Regents of the University of Texas SystemInventors: Jose Luis Cruz-Campa, Xiaowang Zhou, David Zubia
-
Patent number: 8518737Abstract: The present invention provides a reaction chamber to monitor a metal ion in solution during the formation of a metal-sulfide layer on a substrate. The reaction chamber houses a solution of an ammonium ion, a metal ion and a buffer. The reaction chamber includes an anion-selective electrode in the solution to monitor the metal ion that measures the metal ion during metal-ammonium complex formation, metal-thiourea complex formation, metal sulfide composition formation, metal sulfide layer formation or a combination thereof.Type: GrantFiled: August 31, 2011Date of Patent: August 27, 2013Assignee: Board of Regents, The University of Texas SystemInventors: David Zubia, Rafael Ordonez
-
Publication number: 20120058596Abstract: The present invention provides a reaction chamber to monitor a metal ion in solution during the formation of a metal-sulfide layer on a substrate. The reaction chamber houses a solution of an ammonium ion, a metal ion and a buffer. The reaction chamber includes an anion-selective electrode in the solution to monitor the metal ion that measures the metal ion during metal-ammonium complex formation, metal-thiourea complex formation, metal sulfide composition formation, metal sulfide layer formation or a combination thereof.Type: ApplicationFiled: August 31, 2011Publication date: March 8, 2012Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: David Zubia, Rafael Ordonez
-
Patent number: 6841456Abstract: A method for fabricating thin films of an icosahedral boride on a silicon carbide (SiC) substrate is provided. Preferably the icosahedral boride layer is comprised of either boron phosphide (B12P2) or boron arsenide (B12As2). The provided method achieves improved film crystallinity and lowered impurity concentrations. In one aspect, an epitaxially grown layer of B12P2 with a base layer or substrate of SiC is provided. In another aspect, an epitaxially grown layer of B12As2 with a base layer or substrate of SiC is provided. In yet another aspect, thin films of B12P2 or B12As2 are formed on SiC using CVD or other vapor deposition means. If CVD techniques are employed, preferably the deposition temperature is above 1050° C., more preferably in the range of 1100° C. to 1400° C., and still more preferably approximately 1150° C.Type: GrantFiled: April 17, 2003Date of Patent: January 11, 2005Inventors: Stephen D. Hersee, Ronghua Wang, David Zubia, Terrance L. Aselage, David Emin
-
Publication number: 20040005768Abstract: A method for fabricating thin films of an icosahedral boride on a silicon carbide (SiC) substrate is provided. Preferably the icosahedral boride layer is comprised of either boron phosphide (B12P2) or boron arsenide (B12As2). The provided method achieves improved film crystallinity and lowered impurity concentrations. In one aspect, an epitaxially grown layer of B12P2 with a base layer or substrate of SiC is provided. In another aspect, an epitaxially grown layer of B12As2 with a base layer or substrate of SiC is provided. In yet another aspect, thin films of B12P2 or B12As2 are formed on SiC using CVD or other vapor deposition means. If CVD techniques are employed, preferably the deposition temperature is above 1050° C., more preferably in the range of 1100° C. to 1400° C., and still more preferably approximately 1150° C.Type: ApplicationFiled: April 17, 2003Publication date: January 8, 2004Inventors: Stephen D. Hersee, Ronghua Wang, David Zubia, Terrance L. Aselage, David Emin
-
Patent number: 6596377Abstract: A new and useful technique for growing an epilayer onto a substrate is provided. An epilayer is grown on a substrate by (a) providing a patterned substrate comprising a plurality of isolated nanoscale nucleation sites, and (b) growing an epilayer selectively on the nanoscale nucleation sites, in a manner which localizes strain at the substrate-epilayer interface, and enables strain to reduce as the thickness of the epilayer increases.Type: GrantFiled: March 27, 2000Date of Patent: July 22, 2003Assignee: Science & Technology Corporation @ UNMInventors: Stephen D. Hersee, David Zubia, Steven R. J. Brueck, Saleem H. Zaidi