Abstract: Process for integrating in a same MOS technology devices with different threshold voltages. Simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area. Selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions.

Abstract: A semiconductor device including a substrate having a first conductivity type on which are formed first and second epitaxial layers of the same conductivity type of the substrate. The semiconductor device also includes a first diffused region having a second conductivity type formed in a first portion of the first and second epitaxial layers. Said first diffused region defines a first junction with said first and second epitaxial layers. The semiconductor device also comprises an edge structure having the second conductivity type formed in a second portion of the first and second epitaxial layers. The edge structure includes a second diffused region having the second conductivity type formed in the first and second epitaxial layers, said second diffused region defining a second junction with said first and second epitaxial layers.