Patents by Inventor Davide Brambilla
Davide Brambilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131198Abstract: The present disclosure relates to ratiometric detection compositions comprising a reference dye and a sensor dye that are PEGylated dyes, and microneedles comprising said compositions. The present disclosure further relates to methods of ratiometric detection/measurement/monitoring of analytes in a subject using the ratiometric detection compositions of the present disclosure.Type: ApplicationFiled: July 24, 2023Publication date: April 25, 2024Inventors: Davide Brambilla, Samuel Babity
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Patent number: 11007282Abstract: This invention describes compositions comprising indocyanine green and poly(N-vinylpyrrolidone) and methods of making the same as well as applications thereof for diagnostic and therapeutic uses. One of those applications is the structural and functional assessment of the lymphatic system by fluorescence imaging.Type: GrantFiled: May 10, 2016Date of Patent: May 18, 2021Assignee: DICRONIS SAGLInventors: Jean-Christophe Leroux, Michael Detmar, Davide Brambilla, Steven Proulx
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Publication number: 20180110882Abstract: This invention describes compositions comprising indocyanine green and poly(N-vinylpyrrolidone) and methods of making the same as well as applications thereof for diagnostic and therapeutic uses. One of those applications is the structural and functional assessment of the lymphatic system by fluorescence imaging.Type: ApplicationFiled: May 10, 2016Publication date: April 26, 2018Inventors: Jean-Christophe LEROUX, Michael DETMAR, Davide BRAMBILLA, Steven PROULX
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Patent number: 7230482Abstract: A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.Type: GrantFiled: December 23, 2004Date of Patent: June 12, 2007Assignee: STMicroelectronics S.r.l.Inventors: Fabio Chelli, Davide Brambilla
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Publication number: 20060022749Abstract: A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.Type: ApplicationFiled: December 23, 2004Publication date: February 2, 2006Applicant: STMicroelectronics S.r.l.Inventors: Fabio Chelli, Davide Brambilla
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Publication number: 20050174705Abstract: In a device that includes a pair of closed-loop voltage regulators each including an input transconductance stage receiving a reference voltage and a feedback voltage, an intermediate transresistance stage, an output buffer operatively in cascade for generating on an output node the regulated output voltage and negative feedback means for providing the feedback voltage to the input stage, the method includes a circuit that limits the difference between two output regulated voltages. The limiting circuit includes a differential transconductance amplifier input with voltages proportional to the output voltages of the regulators or obtained by adding an offset voltage to the output voltage of the regulators for injecting in, or draining from, an input node of the intermediate stage of one of the regulators, a current as a function of the relative unbalance of the differential transconductance amplifier.Type: ApplicationFiled: February 11, 2005Publication date: August 11, 2005Applicant: STMicroelectronics S.r.l.Inventors: Davide Brambilla, Daniela Nebuloni
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Patent number: 6437606Abstract: A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.Type: GrantFiled: October 13, 2000Date of Patent: August 20, 2002Assignee: STMicroelectronics S.r.l.Inventors: Danilo Ranieri, Davide Brambilla, Edoardo Botti, Luca Celant
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Patent number: 6429741Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.Type: GrantFiled: June 12, 2001Date of Patent: August 6, 2002Assignee: STMicroelectronics, S.r.l.Inventors: Davide Brambilla, Daniela Nebuloni, Mauro Cleris
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Patent number: 6392393Abstract: A method of voltage driving a load using a controlled current includes providing a negative feedback of an output current, measuring the output current on a collector of an output transistor of an output stage, comparing the measured output current with an input current to define a current difference, and providing the current difference at a base of the output transistor to provide the voltage driving.Type: GrantFiled: June 15, 2000Date of Patent: May 21, 2002Assignee: STMicroelectronics S.R.L.Inventors: Davide Brambilla, Giovanni Capodivacca, Danilo Ranieri
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Patent number: 6384645Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch.Type: GrantFiled: April 2, 2001Date of Patent: May 7, 2002Assignee: STMicroelectronics S.r.l.Inventors: Davide Brambilla, Mauro Cleris
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Publication number: 20010050593Abstract: An amplifier having an input; an output supplying an output signal, and a feedback network connected between the input and the output, and a distortion detection circuit. The feedback network includes a first and a second feedback element arranged in series and forming an intermediate node supplying an intermediate signal in phase with the output signal in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit includes a phase-comparating circuit which detects the phase of the output signal and of the intermediate signal, and generates a distortion-indicative signal, when the intermediate signal is in phase opposition with respect to the output signal.Type: ApplicationFiled: June 12, 2001Publication date: December 13, 2001Inventors: Davide Brambilla, Daniela Nebuloni, Mauro Cleris
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Publication number: 20010043096Abstract: An integrated circuit for producing a small slope voltage ramp includes a circuit for generating a periodic triangular current signal, and a circuit for generating, at the beginning of each period of the triangular signal, a pulse of a certain duration which is much smaller than the period of the triangular signal. A control loop is input at a node with the triangular current signal and produces the desired slow voltage ramp on the output node. The control loop includes a first hold circuit coupled to the input node via a first switch controlled by the pulse, and a transconductance operational amplifier, whose inputs are respectively coupled to the input node and to the output node. Also, the control loop includes a second hold circuit coupled to the output of the operational transconductance amplifier via a second switch controlled in a complementary manner with respect to the first switch.Type: ApplicationFiled: April 2, 2001Publication date: November 22, 2001Applicant: STMicroelectronics S.r.l.Inventors: Davide Brambilla, Mauro Cleris
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Patent number: 6307434Abstract: A circuit for ensuring a complete saturation of both operational amplifiers of a single-input bridge amplifier is provided. A voltage divider is connected between the inverting inputs of the two amplifiers and a saturation current signal is injected on the intermediate node of the voltage divider. Such a saturation current signal is obtained through dedicated sensing devices of the state of saturation reached by the transistors of the output stages of both amplifiers of the single-input bridge amplifier.Type: GrantFiled: December 14, 1999Date of Patent: October 23, 2001Assignee: STMicroelectronics S.r.l.Inventors: Davide Brambilla, Giovanni Capodivacca
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Patent number: 6255904Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.Type: GrantFiled: December 14, 1999Date of Patent: July 3, 2001Assignee: STMicroelectronics S.r.l.Inventors: Giovanni Capodivacca, Davide Brambilla
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Patent number: 6072359Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2).Type: GrantFiled: June 30, 1998Date of Patent: June 6, 2000Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Davide Brambilla, Daniela Nebuloni, Giorgio Rossi, Sergio Lecce
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Patent number: 5942783Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.Type: GrantFiled: January 31, 1996Date of Patent: August 24, 1999Assignee: STMicroelectronics, S.r.l.Inventors: Davide Brambilla, Edoardo Botti, Paolo Ferrari
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Patent number: 5874852Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2).Type: GrantFiled: August 30, 1996Date of Patent: February 23, 1999Assignee: SGS-Thomson Microelectronics, S.r.l.Inventors: Davide Brambilla, Daniela Nebuloni, Giorgio Rossi, Sergio Lecce
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Patent number: 5801536Abstract: A method of checking an integrity of an electric power connection between a contact pad of an integrated circuit and a corresponding contact pin in an electronic power device, wherein the electronic power device includes at least one final power stage powered from the respective discrete contact pad connected by means of the electric power connection to the respective contact pin. The method of checking is accomplished by providing a resistive connection between two contact pads of the electronic power device bringing the at least one final power stage, powered from the first contact pad, to a conduction state, measuring the potential difference between the two contact pins connected to the two contact pads, and comparing the potential difference with a predetermined nominal potential difference.Type: GrantFiled: December 19, 1995Date of Patent: September 1, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Davide Brambilla, Giovanni Capodivacca, Fabrizio Stefani
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Patent number: 5210481Abstract: Voltage/current characteristics control circuit particularly for protecting power transistors, which comprises at least one power transistor; the emitter terminal of a first transistor is directly connected to the output of the power transistor; the emitter terminal of a second transistor is connected to the first terminal of the power transistor by means of a first resistor. The collector terminal and the base terminal of the first transistor are connected to a current source. The base terminal of the first transistor is connected to the base terminal of the second transistor, and the circuit furthermore comprises a protection circuitry. The circuitry is connected to the collector terminal of the second transistor through a differential stage which comprises a third transistor and a fourth transistor; the third transistor and fourth transistor have a respective second resistor and third resistor arranged in series.Type: GrantFiled: December 17, 1991Date of Patent: May 11, 1993Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Davide Brambilla, Edoardo Botti
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Patent number: 5204638Abstract: Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.Type: GrantFiled: December 17, 1991Date of Patent: April 20, 1993Assignee: SGS-Thomson Microelectronics S.r.l.Inventors: Davide Brambilla, Fabrizio Stefani