Patents by Inventor Davide M. Santo

Davide M. Santo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error detection and communication of an error location in multi-processor data processing system having processors operating in Lockstep
    Patent number: 8090984
    Abstract: A system and method are provided. The system comprises a first and second processor, and a cross-signaling interface. The first processor executes instructions. The second processor executes the instructions in lockstep with the first processor. The cross-signaling interface is coupled between the first and second processors and is for signaling both an unanticipated altered state a location of the unanticipated altered state in the first processor to the second processor to cause the second processor to emulate the unanticipated altered state in lockstep with the first processor. The method comprises: executing instructions in a first processor; executing the instructions in a second processor in lockstep with the first processor; detecting an error condition in the first processor; transmitting information about the error condition to the second processor; processing the error condition in the first processor; and causing the first and second processor to emulate the error condition in lockstep.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: January 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Michael J. Rochford, Davide M. Santo
  • ERROR DETECTION IN A MULTI-PROCESSOR DATA PROCESSING SYSTEM
    Publication number: 20100146335
    Abstract: A system and method are provided. The system comprises a first and second processor, and a cross-signaling interface. The first processor executes instructions. The second processor executes the instructions in lockstep with the first processor. The cross-signaling interface is coupled between the first and second processors and is for signaling both an unanticipated altered state a location of the unanticipated altered state in the first processor to the second processor to cause the second processor to emulate the unanticipated altered state in lockstep with the first processor. The method comprises: executing instructions in a first processor; executing the instructions in a second processor in lockstep with the first processor; detecting an error condition in the first processor; transmitting information about the error condition to the second processor; processing the error condition in the first processor; and causing the first and second processor to emulate the error condition in lockstep.
    Type: Application
    Filed: December 10, 2008
    Publication date: June 10, 2010
    Inventors: William C. Moyer, Michael J. Rochford, Davide M. Santo