Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.

Abstract: A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.

Abstract: A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.

Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.

Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.

Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.

Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.

Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.

Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.