Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

Abstract: A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.

Abstract: A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.

Abstract: A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.

Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

Abstract: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Abstract: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder.

Abstract: A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.

Abstract: A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.

Abstract: A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.

Abstract: A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder.

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.

Abstract: A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.

Abstract: A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.

Abstract: Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.

Abstract: A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.

Abstract: A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.