Abstract: A method of measuring a phase difference for use in a phase locked loop (PLL) that includes a binary phase detector (BPD), a time-to-digital converter (TDC) and a signal generator, the phase difference being that between a reference signal and a generated signal output from the signal generator. The method includes inputting the reference signal and the generated signal into the TDC; measuring the magnitude of the phase difference at the TDC; if the measured magnitude of the phase difference is less than a threshold value, operating the PLL according to a first operational mode in which the output of the BPD controls the signal generator; and if the measured magnitude of the phase difference is greater than the threshold value, operating the PLL according to a second operational mode in which the output of the TDC and the BPD controls the signal generator.

Abstract: A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.

Abstract: A capacitive divider structure, comprising: a first plurality of capacitive devices, each being selectively controlled in accordance with a first input control signal so as to alter the effective capacitance of the capacitive divider structure by a first amount; a second plurality of capacitive devices coupled in parallel with the first plurality of capacitive devices, each being selectively controlled in accordance with a second input control signal so as to alter the effective capacitance of the capacitive divider structure by a second amount; and at least one series capacitive device arranged in series with the second plurality of capacitive devices, such that the second amount is less than the first amount.

Abstract: A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.

Abstract: A method of measuring a phase difference for use in a phase locked loop (PLL) that includes a binary phase detector (BPD), a time-to-digital converter (TDC) and a signal generator, the phase difference being that between a reference signal and a generated signal output from the signal generator. The method includes inputting the reference signal and the generated signal into the TDC; measuring the magnitude of the phase difference at the TDC; if the measured magnitude of the phase difference is less than a threshold value, operating the PLL according to a first operational mode in which the output of the BPD controls the signal generator; and if the measured magnitude of the phase difference is greater than the threshold value, operating the PLL according to a second operational mode in which the output of the TDC and the BPD controls the signal generator.

Abstract: A phase locked loop that includes a signal generator arranged to output a feedback signal, a first phase detector arranged to detect a phase difference between the feedback signal and a reference signal and to output a first phase detect signal in dependence on that detection, a second phase detector arranged to detect a phase difference between the feedback signal and a delayed version of the reference signal or between the reference signal and a delayed version of the feedback signal and to output a second phase detect signal in dependence on that detection, and an adjustor. The adjustor is arranged to determine which of the first and second phase detect signals commutes first and to alter the frequency of the feedback signal in dependence on the result of the determination.