Abstract: Network communication apparatus for connection to a computer that includes a host processor, a host memory and at least first and second root ports. The apparatus includes a network port, for connection to a packet communication network, and first and second host bus interfaces, for connection via respective first and second peripheral component buses to the first and second root ports, respectively. Packet processing logic is coupled between the network port and the first and second host bus interfaces and includes first and second direct memory access (DMA) engines to read data from the host memory via the first and second root ports, respectively, for transmission via the network port, while exposing the network port to the host computer only through the first host bus interface.

Abstract: Network communication apparatus for connection to a computer that includes a host processor, a host memory and at least first and second root ports. The apparatus includes a network port, for connection to a packet communication network, and first and second host bus interfaces, for connection via respective first and second peripheral component buses to the first and second root ports, respectively. Packet processing logic is coupled between the network port and the first and second host bus interfaces and includes first and second direct memory access (DMA) engines to read data from the host memory via the first and second root ports, respectively, for transmission via the network port, while exposing the network port to the host computer only through the first host bus interface.

Abstract: A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission time. A computer based system and method for GPU-initiated communication over a 5G data network may include allocating one or more memory buffers in GPU memory; performing at least one 5G signal processing procedure by a GPU; preparing descriptors for a plurality of packets, where each packet includes allocated memory buffers, and where the descriptors provide scheduling instructions for the packets; and triggering the sending of packets over the network based on prepared descriptors.

Abstract: A computer based system and method for sending data packets over a data network may include: preparing data packets and packet descriptors on one or more graphical processing units (GPUs); associating packets with a packet descriptor, which may determine a desired transmission time of the packets associated with that descriptor; receiving an indication of a clock time; and physically transmitting packets via an output interface, at a clock time corresponding to the desired transmission time. A computer based system and method for GPU-initiated communication over a 5G data network may include allocating one or more memory buffers in GPU memory; performing at least one 5G signal processing procedure by a GPU; preparing descriptors for a plurality of packets, where each packet includes allocated memory buffers, and where the descriptors provide scheduling instructions for the packets; and triggering the sending of packets over the network based on prepared descriptors.

Abstract: A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described.

Abstract: A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described.