Patents by Inventor Davide Sarta

Davide Sarta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus use with interrupts
    Patent number: 10255207
    Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: April 9, 2019
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Davide Sarta, Ignazio Antonino Urzi
  • Memory manager
    Patent number: 9164903
    Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 20, 2015
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Davide Sarta
  • METHOD AND APPARATUS USE WITH INTERRUPTS
    Publication number: 20150127865
    Abstract: A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 7, 2015
    Inventors: Davide Sarta, Ignazio Antonino Urzi
  • Arrangement, method, integrated circuit and device for routing requests
    Patent number: 8764874
    Abstract: A request routing circuit includes m inputs for receiving m input request signals and n outputs for outputting a set of n output request signals. A routing subsystem within the request routing circuit is provided between the m inputs and the n outputs and comprises k inputs and n outputs, where m is greater than k, and where the routing subsystem is configured to operate over a plurality (m/k, rounded up to the next integer) of cycles to provide the set of n output request signals based on the m inputs to the n outputs.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Davide Sarta, David Smith
  • ARRANGEMENT, METHOD, INTEGRATED CIRCUIT AND DEVICE FOR ROUTING REQUESTS
    Publication number: 20130097343
    Abstract: A request routing circuit includes m inputs for receiving m input request signals and n outputs for outputting a set of n output request signals. A routing subsystem within the request routing circuit is provided between the m inputs and the n outputs and comprises k inputs and n outputs, where m is greater than k, and where the routing subsystem is configured to operate over a plurality (m/k, rounded up to the next integer) of cycles to provide the set of n output request signals based on the m inputs to the n outputs.
    Type: Application
    Filed: September 10, 2012
    Publication date: April 18, 2013
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: Davide Sarta, David Smith