Patents by Inventor Davide Tesi
Davide Tesi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7052179Abstract: An integrated temperature sensor having a first PNP-type bipolar transistor diode-connected between a first terminal and a second terminal of the sensor intended to be connected to a reference supply rail; a resistive element and a second diode-connected PNP-type bipolar transistor, connected in series between a third terminal of the sensor and the second terminal, the second bipolar transistor being larger than the first one; a current-to-voltage conversion element connected between a fourth terminal and the second terminal, the first and third terminals being intended to be connected by a voltage-copying element and the first, second, and fourth terminals being intended to each receive an identical current.Type: GrantFiled: December 19, 2002Date of Patent: May 30, 2006Assignee: STMicroelectronics S.A.Inventor: Davide Tesi
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Patent number: 7029171Abstract: A digital integrated circuit temperature sensor including an analog-to-digital converter providing a binary word representative of a temperature internal to the integrated circuit, and a circuit for providing an analog voltage representative of the circuit temperature and for generating a reference voltage for the analog-to-digital converter. The present invention especially applies to the testing of integrated circuits and to the control of their frequency and/or of their operating temperature according to their internal temperature.Type: GrantFiled: October 9, 2003Date of Patent: April 18, 2006Assignee: STMicroelectronics S.A.Inventors: Davide Tesi, Ugo Zampieri
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Patent number: 6946825Abstract: A circuit for generating a reference voltage of bandgap type. The circuit includes a current mirror assembly of cascode type including, from a high supply rail, at least two parallel branches of P-channel MOS transistors. The circuit also includes a bipolar assembly in series with one of the branches of the mirror assembly down to a low supply rail, formed of two parallel branches each including, in series, a diode-connected bipolar transistor and, respectively, one resistor and two resistors. The circuit also includes a differential amplifier for balancing the currents in the two branches of the bipolar assembly, the reference voltage being provided by the terminal of interconnection of the mirror assembly with the bipolar assembly.Type: GrantFiled: October 9, 2003Date of Patent: September 20, 2005Assignee: STMicroelectronics S.A.Inventor: Davide Tesi
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Patent number: 6879506Abstract: A memory element in an integrated circuit includes several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.Type: GrantFiled: May 1, 2003Date of Patent: April 12, 2005Assignee: STMicroelectronics S.A.Inventors: Philippe Lebourg, Davide Tesi
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Publication number: 20040075487Abstract: A circuit for generating a reference voltage of bandgap type, comprising: a current mirror assembly of cascode type comprising, from a high supply rail, at least two parallel branches of P-channel MOS transistors; a bipolar assembly in series with one of said branches of the mirror assembly down to a low supply rail, formed of two parallel branches each comprising, in series, a diode-connected bipolar transistor and, respectively, one resistor and two resistors; and a differential amplifier for balancing the currents in the two branches of the bipolar assembly, the reference voltage being provided by the terminal of interconnection of the mirror assembly with the bipolar assembly.Type: ApplicationFiled: October 9, 2003Publication date: April 22, 2004Inventor: Davide Tesi
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Publication number: 20040071183Abstract: A digital integrated circuit temperature sensor comprising an analog-to-digital converter providing a binary word representative of a temperature internal to the integrated circuit, and a circuit for providing an analog voltage representative of the circuit temperature and for generating a reference voltage for the analog-to-digital converter. The present invention especially applies to the testing of integrated circuits and to the control of their frequency and/or of their operating temperature according to their internal temperature.Type: ApplicationFiled: October 9, 2003Publication date: April 15, 2004Inventors: Davide Tesi, Ugo Zampieri
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Publication number: 20030214863Abstract: A memory element in an integrated circuit including several levels of conductive materials separated by insulating levels, each of which is capable of being crossed by conductive vias of an intercalary via level, and at least two connection rails, including several assemblies of successive interconnected areas and vias, a first assembly being formed of a zigzag running from a first metal level to a last metal level and back to the first metal level between a first end and a second end, each of the other assemblies being connected to one of the connection rails, the first end of the zigzag being connected to an initial assembly among the other assemblies.Type: ApplicationFiled: May 1, 2003Publication date: November 20, 2003Inventors: Philippe Lebourg, Davide Tesi
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Publication number: 20030123520Abstract: An integrated temperature sensor having a first PNP-type bipolar transistor diode-connected between a first terminal and a second terminal of the sensor intended to b connected to a reference supply rail; a resistive element and a second diode-connected PNP-type bipolar transistor, connected in series between a third terminal of the sensor and the second terminal, the second bipolar transistor being larger than the first one; a current-to-voltage conversion element connected between a fourth terminal and the second terminal, the first and third terminals being intended to be connected by a voltage-copying element and the first, second, and fourth terminals being intended to each receive an identical current.Type: ApplicationFiled: December 19, 2002Publication date: July 3, 2003Inventor: Davide Tesi
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Patent number: 6505294Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.Type: GrantFiled: November 16, 2001Date of Patent: January 7, 2003Assignee: STMicroelectronics S.r.l.Inventors: Francesco Pappalardo, Davide Tesi, Francesco Nino Mammoliti, Francesco Bombaci
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Patent number: 6389528Abstract: A processor is provided with a set of instructions formed in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the normal path in which normal instructions are interpreted. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.Type: GrantFiled: December 23, 1998Date of Patent: May 14, 2002Assignee: STMicroelectronics S.r.l.Inventors: Francesco Pappalardo, Davide Tesi, Francesco Nino Mammoliti, Francesco Bombaci
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Publication number: 20020035679Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.Type: ApplicationFiled: November 16, 2001Publication date: March 21, 2002Applicant: STMicroelectronics S.r.I.Inventors: Francesco Pappalardo, Davide Tesi, Francesco Nino Mammoliti, Francesco Bombaci
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Publication number: 20010023481Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.Type: ApplicationFiled: December 23, 1998Publication date: September 20, 2001Inventors: FRANCESCO PAPPALARDO, DAVIDE TESI, FRANCESCO NINO MAMMOLITI, FRANCESCO BOMBACI
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Patent number: 6199056Abstract: An apparatus over or under approximates the result of dividing a binary number representing an integer 2n. The division by 2n is performed by truncating the n least significant bits of the integer. In order to over or under approximate the result, the nth truncated bit, i.e., the most significant bit of the n-truncated less significant bits, is added to the integer represented by the remaining non-truncated bits.Type: GrantFiled: October 19, 1998Date of Patent: March 6, 2001Assignee: Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventors: Francesco Pappalardo, Vincenzo Matranga, Davide Tesi, Dario Di Bella
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Patent number: 5915247Abstract: A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and an axis of the universe of discourse. Further, the method includes storing a second distance between the position of the vertex and point of intersection between right side of the triangle and the axis of the universe of discourse. The present invention furthermore relates to a circuit for calculating a grade of membership of an antecedent of a fuzzy rule, and is adapted to fuzzyfy an input variable by adopting the geometric proportions that occur between homologous sides of similar triangles defined by the position of the input value in the universe of discourse.Type: GrantFiled: September 26, 1997Date of Patent: June 22, 1999Assignee: Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventors: Francesco Pappalardo, Vincenzo Matranga, Davide Tesi, Dario Di Bella
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Patent number: 5875438Abstract: A method for storing a membership function, include storing a position of a vertex of a triangle that defines the membership function in a universe of discourse and storing a first distance between the position of the vertex a point of intersection between a left side of the triangle and an axis of the universe of discourse. Further, the method includes storing a second distance between the position of the vertex and point of intersection between right side of the triangle and the axis of the universe of discourse. The present invention furthermore relates to a circuit for calculating a grade of membership of an antecedent of a fuzzy rule, and is adapted to fuzzify an input variable by adopting the geometric proportions that occur between homologous sides of similar triangles defined by the position of the input value in the universe of discourse.Type: GrantFiled: March 26, 1996Date of Patent: February 23, 1999Assignee: Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventors: Francesco Pappalardo, Vincenzo Matranga, Davide Tesi, Dario Di Bella