Abstract: A pre-driving stage drives one or more Field Effect Transistors in a power stage driving a load. A method for measuring current flowing in the Field Effect Transistors includes: measuring drain to source voltages of the one or more Field Effect Transistor; and measuring an operating temperature of the one or more Field Effect Transistor. The current flowing in the Field Effect Transistors is measured by: calculating the respective on drain to source resistance at the operating temperature as a function of the measured operating temperature and obtaining the current value as a ratio of the respective measured drain to source voltage over the calculated drain to source resistance at the operating temperature.

Abstract: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Abstract: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Abstract: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Abstract: A bit-line selection circuit for a memory device includes a decoding line and a dummy line: The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal.

Abstract: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Abstract: A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference current path identical to the at least one reference current path and in parallel therewith. A connection circuit connects in a mutually exclusive way control terminals of the decoding transistor and reference cell of the at least one reference current path to a node or control terminals of the decoding transistor and reference cell of the at least one redundant reference current path to the node. The connecting is based upon a logic signal. A window comparator is coupled to the reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputs the logic signal for the connection circuit based upon the comparison.

Abstract: A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Each of the cells has a gate terminal biased in the programming phase with a predetermined voltage value through operation of charge pump voltage regulators. A first and a second regulation stage, which are structurally independent, are responsible for the programming and soft programming phase respectively. The first stage generates a supply voltage for the second stage.

Abstract: A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference current path identical to the at least one reference current path and in parallel therewith. A connection circuit connects in a mutually exclusive way control terminals of the decoding transistor and reference cell of the at least one reference current path to a node or control terminals of the decoding transistor and reference cell of the at least one redundant reference current path to the node. The connecting is based upon a logic signal. A window comparator is coupled to the reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputs the logic signal for the connection circuit based upon the comparison.

Abstract: A bit-line selection circuit for a memory device includes a decoding line and a dummy line. The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal.

Abstract: A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Each of the cells has a gate terminal biased in the programming phase with a predetermined voltage value through operation of charge pump voltage regulators. A first and a second regulation stage, which are structurally independent, are responsible for the programming and soft programming phase respectively. The first stage generates a supply voltage for the second stage.

Abstract: An output buffer for causing a voltage (Vout) of an integrated circuit output line (OUT,OUT_PAD) to switch from a voltage of a first voltage line (VDD) to a voltage of a second voltage line (GND) and vice versa, comprises a current path switch circuit (111a,111b) activatable for causing a prescribed current (Is) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated (Ic1) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by the first and second voltage lines is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.

Abstract: A negative charge pump circuit includes a cascade connection of a plurality of charge pump stages, each stage including at least a charge capacitance and a pass transistor driven by a corresponding phase signal. An input stage may be coupled to an input reference potential. An output stage may include an output terminal for generating a first pumped voltage. In addition, the charge pump circuit may further include a second output stage connected downstream to the input stage and including a second output terminal for generating a second pumped potential. The architecture may also be implemented in positive charge pump circuits.

Abstract: A negative charge pump circuit includes a cascade connection of a plurality of charge pump stages, each stage including at least a charge capacitance and a pass transistor driven by a corresponding phase signal. An input stage may be coupled to an input reference potential. An output stage may include an output terminal for generating a first pumped voltage. In addition, the charge pump circuit may further include a second output stage connected downstream to the input stage and including a second output terminal for generating a second pumped potential. The architecture may also be implemented in positive charge pump circuits.

Abstract: An output buffer for causing a voltage (Vout) of an integrated circuit output line (OUT,OUT13 PAD) to switch from a voltage of a first voltage line (VDD) to a voltage of a second voltage line (GND) and vice versa, comprises a current path switch circuit (111a,111b) activatable for causing a prescribed current (Is) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated (Ic1) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by the first and second voltage lines is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.