Patents by Inventor Davinder Aggarwal
Davinder Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9990458Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.Type: GrantFiled: February 17, 2016Date of Patent: June 5, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Davinder Aggarwal, Vaibhav A. Ruparelia, Neha Singh, Janakiraman Viraraghavan
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Publication number: 20160162628Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.Type: ApplicationFiled: February 17, 2016Publication date: June 9, 2016Inventors: Davinder AGGARWAL, Vaibhav A. RUPARELIA, Neha SINGH, Janakiraman VIRARAGHAVAN
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Patent number: 9292652Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.Type: GrantFiled: May 6, 2014Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Davinder Aggarwal, Vaibhav A. Ruparelia, Neha Singh, Janakiraman Viraraghavan
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Publication number: 20150324510Abstract: A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle.Type: ApplicationFiled: May 6, 2014Publication date: November 12, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Davinder AGGARWAL, Vaibhav A. RUPARELIA, Neha SINGH, Janakiraman VIRARAGHAVAN
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Patent number: 8875064Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Davinder Aggarwal, Vibhor Jain, Janakiraman Viraraghavan
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Publication number: 20140282329Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Davinder AGGARWAL, Vibhor JAIN, Janakiraman VIRARAGHAVAN
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Patent number: 7774682Abstract: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.Type: GrantFiled: February 15, 2008Date of Patent: August 10, 2010Inventors: Ashish Kumar Goel, Namerita Khanna, Davinder Aggarwal
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Patent number: 7606969Abstract: An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.Type: GrantFiled: December 6, 2004Date of Patent: October 20, 2009Inventors: Davinder Aggarwal, Ashish Kumar Goel, Namerita Khanna
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Publication number: 20080215935Abstract: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.Type: ApplicationFiled: February 15, 2008Publication date: September 4, 2008Inventors: Ashish Kumar Goel, Namerita Khanna, Davinder Aggarwal
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Patent number: 7350134Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ānā. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.Type: GrantFiled: September 18, 2003Date of Patent: March 25, 2008Assignee: Sicronic Remote KG, LLCInventors: Ashish Kumar Goel, Namerita Khanna, Davinder Aggarwal
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Patent number: 7271616Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.Type: GrantFiled: July 26, 2005Date of Patent: September 18, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Ashish Kumar Goel, Davinder Aggarwal
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Patent number: 7157935Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.Type: GrantFiled: September 30, 2004Date of Patent: January 2, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Ashish K. Goel, Davinder Aggarwal
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Publication number: 20060022700Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.Type: ApplicationFiled: July 26, 2005Publication date: February 2, 2006Inventors: Ashish Goel, Davinder Aggarwal
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Publication number: 20050172070Abstract: An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.Type: ApplicationFiled: December 6, 2004Publication date: August 4, 2005Applicant: STMicroelectronics Pvt. Ltd.Inventors: Davinder Aggarwal, Ashish Goel, Namerita Khanna
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Publication number: 20050127943Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.Type: ApplicationFiled: September 30, 2004Publication date: June 16, 2005Applicant: STMicroelectronics PVT. LTD.Inventors: Ashish Goel, Davinder Aggarwal
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Publication number: 20040153923Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ‘n’. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.Type: ApplicationFiled: September 18, 2003Publication date: August 5, 2004Applicant: STMicroelectronics Pvt, Ltd.Inventors: Ashish Kumar Goel, Namerita Khanna, Davinder Aggarwal
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Patent number: RE43081Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.Type: GrantFiled: June 10, 2008Date of Patent: January 10, 2012Assignee: Sicronic Remote KG, LLCInventors: Ashish Kumar Goel, Davinder Aggarwal