Patents by Inventor Davis Moore

Davis Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818380
    Abstract: Disclosed herein are methods, devices and systems of treating dysfunctional biochemical pathway(s) using an individualized treatment plan (ITP) of metabolic support intervention(s) for a patient. The ITP has metabolic support intervention(s) that restore proper functioning of biochemical pathway(s) correcting dysfunction(s) therein. Methods can include determining if the biochemical pathway(s) are dysfunctional by subjecting, via a bio-communication device, the patient to a noninvasive test that includes simulating one or more stimuli that are indicative of the biochemical pathway(s)' s functioning.
    Type: Grant
    Filed: April 26, 2014
    Date of Patent: October 27, 2020
    Inventor: Amy Kathleen Davis Moore
  • Patent number: 10810341
    Abstract: Circuit pin constraints input to a design tool specify respective sets of circuit pins belonging to circuit blocks, and input interface pin constraints specify respective sets of interface pins belonging to instances of an interface circuit. The design tool generates pin solutions, and each pin solution includes pin assignments of the circuit pins to the interface pins. The design tool applies an objective function to the pin solutions and selects one pin solution that satisfies the objective function. The design tool then specifies in a circuit design, connections between the circuit pins and the interface pins according to the selected pin solution.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Xilinx, Inc.
    Inventors: Chirag Ravishankar, Davis Moore
  • Patent number: 10715149
    Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Eric F. Dellinger, Jay T. Young, Brian C. Gaide, Chirag Ravishankar, Davis Moore, Steven P. Young