Abstract: The present disclosure discloses an optical signal transmission device, which includes a light-transmitting body. The front end of the light-transmitting body is provided with a plurality of lenses. The rear end of the light-transmitting body is provided with a plurality of optical fiber holes. Optical fibers are inserted into the optical fiber holes. The optical fiber holes extend towards the interior of the light-transmitting body, and the optical fiber holes are aligned with the lenses one by one. The front side of the light-transmitting body is provided with a plurality of light-emitting chips, and emission ends of the light-emitting chips are aligned with the lenses one by one.

Abstract: There are provided a touch display panel and a touch display device, the touch display panel includes: a display substrate including a plurality of pixel regions and a spacer region spacing the plurality of pixel regions apart from each other; a black matrix located on a light-exiting side of the display substrate, an orthographic projection of the black matrix on the display substrate being located in the spacer region; and a touch control structure layer including a first touch pattern layer located on the light-exiting side of the display substrate, the first touch pattern layer including a plurality of first metal lines, where an orthographic projection of each first metal line on the display substrate is located in the orthographic projection of the black matrix on the display substrate, and the first metal lines are in contact with the black matrix.

Abstract: Techniques discussed herein can facilitate improved security establishment procedures for Vehicle to Everything (V2X) direct connections. Various embodiments are employable at or comprise User Equipment, and can initiate and/or receive V2X security establishment connections wherein a receiving UE can reject the connection based on the initiating UE's capabilities/policy and/or the initiating UE can make the final decision regarding the connection based at least on receiving security policy and capability information from the receiving UE.

Abstract: An example technique for security key derivation in a wireless system includes: receiving a radio resource control (RRC) suspend message from a first node, the RRC suspend message including a first next hop (NH) chaining counter (NCC) value, entering a RRC inactive state, deriving a first node key based on the first NCC value, generating a first uplink message for transmission in the RRC inactive state based on the first node key, and transmitting the first uplink message to a node while in the RRC inactive state.

Abstract: An edge enabler server of an edge data network is configured to receive a verification request comprising an edge enabler client identification (EEC ID), wherein the EEC ID uniquely identifies an edge enabler client (EEC), determine whether the EEC ID is an authorized BEC ID and provide a verification response based on whether the EEC ID is authorized.

Abstract: An inductive plasma acceleration apparatus, comprising a pulse laser assembly, a pulsed discharge assembly, an exciting coil assembly, a solid-state working medium, and a control assembly; the exciting coil assembly is electrically connected to the pulsed discharge assembly such that a strong pulse current is produced in the exciting coil assembly during the discharge process of the pulse discharge assembly, and an inductive pulse electromagnetic field is excited around the exciting coil assembly; the solid-state working medium is positioned on the optical path of a pulse laser emitted by the pulse laser assembly such that the solid-state working medium produces a pulse gas under the ablation action of the pulse laser, and the inductive pulse electromagnetic field is positioned on the circulation gas path of the pulse gas such that the pulse gas can enter the inductive pulse electromagnetic field.

Abstract: A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.

Abstract: A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.

Abstract: A Weil code generator and a method of generating Weil codes with a Weil code length (N) are provided. The Weil code generator includes a plurality of parallel channels (10), a multi-channel read arbiter (20), and two parallel Legendre ROMs (30), which are connected in series. A channel of the plurality of channels stores a current Weil code to demodulate signals from a satellite. The multi-channel read arbiter (20) may determine a win channel from the plurality of channels. The two Legendre ROMs (30) respectively store a first and a second Legendre sequences (LS1, LS2) each having a Legendre sequence length (2N) being double the Weil code length (N). The Weil code generator may generate Weil codes efficiently.

Abstract: An inductive plasma acceleration apparatus, comprising a pulse laser assembly, a pulsed discharge assembly, an exciting coil assembly, a solid state working medium, and a control assembly; the exciting coil assembly is electrically connected to the pulsed discharge assembly such that a strong pulse current is produced in the exciting coil assembly during the discharge process of the pulse discharge assembly, and an inductive pulse electromagnetic field is excited around the exciting coil assembly; the solid state working medium is positioned on the optical path of a pulse laser emitted by the pulse laser assembly such that the solid state working medium produces a pulse gas under the ablation action of the pulse laser, and the inductive pulse electromagnetic field is positioned on the circulation gas path of the pulse gas such that the pulse gas can enter the inductive pulse electromagnetic field.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.

Abstract: Disclosed is an optical fiber connector, including a connecting member, an optical component and an optical fiber. The connecting member is provided with an insertion hole, an optical fiber core of the optical fiber passes through the insertion hole; an end surface of the optical fiber core is flush with an end surface of the connecting member; the optical component is provided with an insertion slot; an end of the connecting member is inserted into the insertion slot; the optical component is provided with a first optical path opening and a second optical path opening; an end of the optical fiber core is aligned with the first optical path opening; a light guiding device for conducting a light beam is disposed between the first optical path opening and the second optical path opening; and a circuit board is disposed below the optical component.

Abstract: A method and a circuit for exciting a crystal oscillation circuit are disclosed herein. The crystal oscillation circuit comprising: charging, with a charging circuit, a voltage-controlled oscillator; providing, with the voltage-controlled oscillator, an exciting signal; blocking, with a direct current blocking capacitor, direct current from the voltage-controlled oscillator to the crystal oscillation circuit; and exciting, with the exciting signal, the crystal oscillation circuit. The circuit for exciting a crystal oscillation circuit, comprising: a charging circuit; a voltage-controlled oscillator coupled to the charging circuit and configured to provide an exciting signal to the crystal oscillation circuit; and a direct current blocking capacitor connected between the voltage-controlled oscillator and the crystal oscillation circuit and configured to block direct current from the voltage-controlled oscillator.

Abstract: A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

Abstract: An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.