Abstract: The present application discloses a solid-phase molding processing method, which includes: heating the heating ring to generate heat in the heating ring; the heat generated by the heating ring is conducted downwardly through the stir body to a shaft shoulder and/or a welding pin of the tool head; driving the stir friction tool to rotate to deform the to-be-processed workpiece to generate friction heat; converging the friction heat with the heat conducted to the tool head to heat and soften the to-be-processed workpiece, to form a plastic deformation flow; and translating the stir friction tool, to make the plastic deformation flow deposited behind the tool head to form a molding portion.

Abstract: A solid state additive method includes: disposing a round consumable rod in a hollow stirring tool; based on a coating layer height, setting a gap between a bottom surface of the hollow stirring tool and a base surface; driving the hollow stirring tool to rotate at a first rotation speed; driving the consumable rod to rotate at a second rotation speed, where the second rotation speed and the first rotation speed are different in angular speed to form a differential, such that the consumable rod rubs against an inner wall of the hollow stirring tool to generate thermal deformation so as to obtain a plastic deformation flow in the hollow stirring tool; pressing the consumable rod downward to enable the plastic deformation flow to be in friction contact with the base surface; translating the hollow stirring tool and stirring the base surface.

Abstract: A friction stir tool cooling method is used for cooling a stirring pin and/or a shaft shoulder of a friction stir tool, it includes that the coolant is introduced into an inlet of a cooling channel, the cooling channel is provided inside the friction stir tool, and the inlet is provided on the side wall of the friction stir tool. The coolant flows downwards to the vicinity of the stirring pin and/or the shaft shoulder, the coolant turns upwards and flows out of the friction stir tool from an outlet. The outlet is provided on the side wall of the friction stir tool.

Abstract: The present disclosure provides an optical structure capable of increasing return loss and a manufacturing method thereof. The optical structure includes: a light transmission body and a plurality of juxtaposed optical fibers, where, a plurality of juxtaposed insertion holes are disposed on the light transmission body; the plurality of optical fibers are inserted into the insertion holes one to one; an inclined end surface inclined at a preset angle relative to a vertical surface is formed at a front end of the optical fibers; a reflection surface aligned with the inclined end surfaces is disposed inside the light transmission body; an avoiding opening for accommodating an optical communication chip is disposed at a front bottom of the light transmission body; a plurality of focusing lenses in one-to-one correspondence with the optical fibers are disposed on a top wall of the avoiding opening.

Abstract: A touch screen panel and an electronic device. A touch integrated circuit layer in the touch screen panel includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and an overlay layer that are stacked. The first metal layer is located between the first insulating layer and the second insulating layer, the second metal layer is located between the second insulating layer and the overlay layer, and the first insulating layer is located between the substrate layer and the first metal layer. The first metal layer and the second metal layer jointly form a touch functional layer, and the touch functional layer at least includes at least one driving electrode unit and a plurality of sensing electrode units. The at least one driving electrode unit is electrically insulated from the plurality of sensing electrode units, and each sensing electrode unit is serrated.

Abstract: The present disclosure discloses an optical signal transmission device, which includes a light-transmitting body. The front end of the light-transmitting body is provided with a plurality of lenses. The rear end of the light-transmitting body is provided with a plurality of optical fiber holes. Optical fibers are inserted into the optical fiber holes. The optical fiber holes extend towards the interior of the light-transmitting body, and the optical fiber holes are aligned with the lenses one by one. The front side of the light-transmitting body is provided with a plurality of light-emitting chips, and emission ends of the light-emitting chips are aligned with the lenses one by one.

Abstract: An inductive plasma acceleration apparatus, comprising a pulse laser assembly, a pulsed discharge assembly, an exciting coil assembly, a solid-state working medium, and a control assembly; the exciting coil assembly is electrically connected to the pulsed discharge assembly such that a strong pulse current is produced in the exciting coil assembly during the discharge process of the pulse discharge assembly, and an inductive pulse electromagnetic field is excited around the exciting coil assembly; the solid-state working medium is positioned on the optical path of a pulse laser emitted by the pulse laser assembly such that the solid-state working medium produces a pulse gas under the ablation action of the pulse laser, and the inductive pulse electromagnetic field is positioned on the circulation gas path of the pulse gas such that the pulse gas can enter the inductive pulse electromagnetic field.

Abstract: A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.

Abstract: A PVT calculation device includes a memory; and one or more processors in communication with the memory configured to perform operations including: receiving observations and ephemerides from satellites to obtain PVT data of the satellites and predicted PVT results of the receiver; setting up observation functions respectively corresponding to the satellites; calculating by a least square solution first estimated PVT results of the receiver based on the observation functions; iteratively eliminating by a Random-Sampling Iterative Kalman Filter (RSIKF) algorithm fault observation functions from the observation functions in an inner cluster until no fault observation functions detected in the inner cluster; calculating by the RSIKF algorithm a second estimated PVT results of the receiver using the observation functions in the inner cluster; and outputting final estimated PVT results of the receiver. The PVT calculation device may calculate the PVT results of the receiver with improved accuracy and stability.

Abstract: A Weil code generator and a method of generating Weil codes with a Weil code length (N) are provided. The Weil code generator includes a plurality of parallel channels (10), a multi-channel read arbiter (20), and two parallel Legendre ROMs (30), which are connected in series. A channel of the plurality of channels stores a current Weil code to demodulate signals from a satellite. The multi-channel read arbiter (20) may determine a win channel from the plurality of channels. The two Legendre ROMs (30) respectively store a first and a second Legendre sequences (LS1, LS2) each having a Legendre sequence length (2N) being double the Weil code length (N). The Weil code generator may generate Weil codes efficiently.

Abstract: An inductive plasma acceleration apparatus, comprising a pulse laser assembly, a pulsed discharge assembly, an exciting coil assembly, a solid state working medium, and a control assembly; the exciting coil assembly is electrically connected to the pulsed discharge assembly such that a strong pulse current is produced in the exciting coil assembly during the discharge process of the pulse discharge assembly, and an inductive pulse electromagnetic field is excited around the exciting coil assembly; the solid state working medium is positioned on the optical path of a pulse laser emitted by the pulse laser assembly such that the solid state working medium produces a pulse gas under the ablation action of the pulse laser, and the inductive pulse electromagnetic field is positioned on the circulation gas path of the pulse gas such that the pulse gas can enter the inductive pulse electromagnetic field.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A low pass filter embedded digital-to-analog converter including a first switch coupled to a first node that is coupled to a fourth switch and a first capacitor, a second switch coupled to a second node that is coupled to the first capacitor and a third switch, a negative input of a first operational amplifier coupled to a third node that is coupled to the third switch and a second capacitor, and an output port of the first operational amplifier coupled to a fourth node that is coupled to the second capacitor and the fourth switch.

Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.

Abstract: A frequency synthesizer, comprises a phase frequency detector to receive a frequency signal and a reference clock, and to output a phase difference according to a phase difference and a frequency difference between the frequency signal and the reference clock; a charge pump to generate a current according to the phase difference; a loop filter to generate a first voltage signal based on the current; a N-path filter each comprising a switch, a path filter and to generate N paths of filtered voltages based on the first voltage; a voltage control oscillator to generate a second voltage signal based on a sum of the N paths of filtered voltages; a frequency divider to generate the frequency signal based on the second voltage signal and a variable frequency dividing ratio; and a Sigma-Delta Modulator to generate the variable frequency dividing ratio based on a digital representation of a frequency fractional value and the reference clock.

Abstract: Disclosed is an optical fiber connector, including a connecting member, an optical component and an optical fiber. The connecting member is provided with an insertion hole, an optical fiber core of the optical fiber passes through the insertion hole; an end surface of the optical fiber core is flush with an end surface of the connecting member; the optical component is provided with an insertion slot; an end of the connecting member is inserted into the insertion slot; the optical component is provided with a first optical path opening and a second optical path opening; an end of the optical fiber core is aligned with the first optical path opening; a light guiding device for conducting a light beam is disposed between the first optical path opening and the second optical path opening; and a circuit board is disposed below the optical component.