Patents by Inventor Dawei Mai

Dawei Mai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12763726
    Abstract: Certain aspects of the present disclosure are directed towards methods and apparatus for oscillating signal generation. An example method generally includes: configuring a first voltage-controlled oscillator (VCO) core of a multi-core VCO based on an oscillating frequency of a second VCO core of the multi-core VCO; and generating, via the second VCO core, an oscillating signal with the oscillating frequency, wherein the first VCO core is off while the oscillating signal is generated via the second VCO core.
    Type: Grant
    Filed: March 19, 2024
    Date of Patent: October 13, 2026
    Assignee: Qualcomm Incorporated
    Inventors: Aaron Curry, Payam Lajevardi, Emanuele Lopelli, Yanan Wu, Dawei Mai, Zhanjun Bai
  • Publication number: 20250300601
    Abstract: Certain aspects of the present disclosure are directed towards methods and apparatus for oscillating signal generation. An example method generally includes: configuring a first voltage-controlled oscillator (VCO) core of a multi-core VCO based on an oscillating frequency of a second VCO core of the multi-core VCO; and generating, via the second VCO core, an oscillating signal with the oscillating frequency, wherein the first VCO core is off while the oscillating signal is generated via the second VCO core.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 25, 2025
    Inventors: Aaron CURRY, Payam LAJEVARDI, Emanuele LOPELLI, Yanan WU, Dawei MAI, Zhanjun BAI
  • Patent number: 11552645
    Abstract: The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1?j?k?L.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 10, 2023
    Assignee: University College Dublin
    Inventors: Dawei Mai, Michael Peter Kennedy
  • Publication number: 20210399734
    Abstract: The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the jth stage is configured to receive as an input the sum of the error of the preceding stage and a high amplitude dither signal derived from the error of the kth stage, where 1?j?k?L.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Inventors: Dawei Mai, Michael Peter Kennedy