Abstract: Some embodiments of this disclosure include apparatuses and methods for supporting integrated access and backhaul (IAB) networks. IAB nodes may be configured to broadcast in-raster and off-raster synchronization signal blocks (SSBs) for establishing communications with mobile devices and/or user equipment (UE). The SSBs may provide control resource set (CORESET) data used for establishing a communication channel between a UE and an IAB node. The CORESET data may be configured to support the broadcast of off-raster SSBs in wireless communication systems. In some embodiments, the in-raster SSB and the off-raster SSB may share the same CORESET. In this case, the IAB may modify a bit pattern of configuration table corresponding to the shared CORESET and broadcast the in-raster SSB and the off-raster SSB while including the modified bit pattern.

Abstract: An antenna apparatus includes a grounding plate, a monopole, a first feeding component, and a second feeding component. A slot on the grounding plate includes a first slot and a second slot that interpenetrate each other, the second slot extends from the first slot to an edge of the grounding plate. The monopole includes a first stub and a second stub extending from the first stub to the second slot, the second stub and the second slot form a feeding structure. The first feeding component is electrically coupled to the grounding plate to feed the feeding structure to excite a first radiation mode of the antenna apparatus. The second feeding component is electrically coupled to the second stub to feed the feeding structure to excite a second radiation mode of the antenna apparatus. Polarizations in the two radiation modes are orthogonal.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: Described herein are various technologies pertaining to delivery of token-authenticated encrypted data. Content descriptor(s) (e.g., playlist(s)) can be modified to facilitate exchange of a token for a decryption key for browser(s) that do not provide logic to manage a flow of the token.

Abstract: A system-on-chip (SoC) for voice and video over data network applications includes a first and a second general purpose processors and a plurality of coprocessors. The coprocessors include: a VCODEC engine for video compression/decompression, a security engine for data encryption/decryption, a network processor for processing data packets, a video scaling controller for scaling up/down video frames, and digital signal coprocessors for signal processing and audio codec. An on-chip shared memory (e.g., SRAM) is coupled to the processors and some of the coprocessors. The SoC also includes: i) a stream controller for controlling various properties of a stream buffer in the shared memory according to a user defined context; ii) a transaction management engine for managing data especially stream transactions in accordance with one or more task queues created by the processors; and iii) a bi-directional stream bus coupled to the shared memory and a plurality of peripheral controllers.