Patents by Inventor Dawn Hopper

Dawn Hopper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9828767
    Abstract: An improved steel stud wall panel which includes a diagonal member able to be placed under tension during installation. The diagonal tension imparts rigidity to the wall panel, preventing warp.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 28, 2017
    Assignee: American Panel Tec Corp.
    Inventors: John Lanzilotta, Dawn Hopper
  • Publication number: 20160115687
    Abstract: An improved steel stud wall panel which includes a diagonal member able to be placed under tension during installation. The diagonal tension imparts rigidity to the wall panel, preventing warp.
    Type: Application
    Filed: October 26, 2015
    Publication date: April 28, 2016
    Applicant: American Panel Tec Corp.
    Inventors: John LANZILOTTA, Dawn HOPPER
  • Publication number: 20140365744
    Abstract: Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Qamrul HASAN, Dawn Hopper, Clifford Alan Zitlaw
  • Patent number: 7977797
    Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: July 12, 2011
    Assignee: Spansion LLC
    Inventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
  • Publication number: 20090294969
    Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.
    Type: Application
    Filed: August 11, 2009
    Publication date: December 3, 2009
    Inventors: Wenmei LI, Angela T. HUI, Dawn HOPPER, Kouros GHANDEHARI
  • Patent number: 7572727
    Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: August 11, 2009
    Assignee: Spansion LLC
    Inventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
  • Patent number: 7361587
    Abstract: The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: April 22, 2008
    Assignee: Spansion, LLC
    Inventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
  • Patent number: 7297592
    Abstract: A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: November 20, 2007
    Assignee: Spansion LLC
    Inventors: Minh Van Ngo, Arvind Halliyal, Tazrien Kamal, Hidehiko Shiraiwa, Rinji Sugino, Dawn Hopper, Pei-Yuan Gao
  • Patent number: 7118967
    Abstract: A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: October 10, 2006
    Assignee: Spansion, LLC
    Inventors: Minh V. Ngo, Ning Cheng, Jeff P. Erhardt, Clarence B. Ferguson, Cyrus Tabery, John Caffall, Tyagamohan Gottipati, Dawn Hopper
  • Patent number: 7071562
    Abstract: Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of ?-Ta thereon.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Dawn Hopper
  • Patent number: 7070911
    Abstract: A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising depositing a first anti-reflective coating having an extinction coefficient above a material, and depositing a second anti-reflective coating having an extinction coefficient above the first anti-reflective coating, such that the first anti-reflective coating and the second anti-reflective coating reduce the formation of standing waves in a photoresist during a lithography process.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn Hopper, Kouros Ghandehari, Minh Van Ngo
  • Patent number: 7005387
    Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.
    Type: Grant
    Filed: November 8, 2003
    Date of Patent: February 28, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn Hopper, Hiroyuki Kinoshita, Christy Woo
  • Patent number: 6969654
    Abstract: A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: November 29, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tuan Duc Pham, Mark T. Ramsbey, Jeffrey A. Shields, Angela T. Hui, Dawn Hopper
  • Patent number: 6900121
    Abstract: Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser thermal annealing the BPSG layer in flowing nitrogen to eliminate or substantially reduce the voids by reflowing the BPSG layer.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 31, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Arvind Halliyal, Dawn Hopper
  • Publication number: 20050101148
    Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.
    Type: Application
    Filed: November 8, 2003
    Publication date: May 12, 2005
    Inventors: Dawn Hopper, Hiroyuki Kinoshita, Christy Woo
  • Patent number: 6867063
    Abstract: A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 15, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Dawn Hopper, Wenmei Li, Angela T. Hui
  • Patent number: 6809402
    Abstract: Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non-volatile transistors and heating during and subsequent to deposition to complete flowing of the B- or BP-HDP oxide into and filling the undercut regions on the sidewall spacers and to densify the B- or BP-HDP oxide.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dawn Hopper, Minh Van Ngo, Atul Gupta, Tyagamohan Gottipati, John Caffall
  • Patent number: 6784095
    Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Minh Van Ngo, Dawn Hopper, Lu You
  • Patent number: 6723634
    Abstract: Semiconductor devices comprising interconnects with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing, in N2 and H2, exposed surfaces of a dielectric layer defining an opening, and then depositing Ta to form a composite layer lining the opening. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing dielectric material, such as F-silicon oxide derived from F-TEOS, impinging a pulsed laser light beam on exposed surfaces of the F-silicon oxide defining the opening in a flow of N2 and H2, and then depositing Ta to form a composite barrier layer comprising graded tantalum nitride and &agr;-Ta lining the opening. Laser thermal annealing in N2 and H2 depletes the exposed silicon oxide surfaces of F while enriching the surfaces with N2. Deposited Ta reacts with the N2 in the N2-enriched surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Dawn Hopper
  • Publication number: 20040063310
    Abstract: Semiconductor devices comprising interconnect with improved adhesion of barrier layers to dielectric layers are formed by laser thermal annealing exposed surfaces of a dielectric layer in an atmosphere of NH3 and N2, and subsequently depositing Ta to form a composite barrier layer. Embodiments include forming a dual damascene opening in an interlayer dielectric comprising F-containing silicon oxide, such as F-containing silicon oxide derived from F-TEOS, laser thermal annealing the exposed silicon oxide surface in NH3 and N2, depositing Ta and then filling the opening with Cu. Laser thermal annealing in NH3 and N2 depletes the exposed silicon oxide surface of F while forming an N2-rich surface region. Deposited Ta reacts with the N2 in the N2-rich surface region to form a composite barrier layer comprising a graded layer of tantalum nitride and a layer of &agr;-Ta thereon.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 1, 2004
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Minh Van Ngo, Dawn Hopper