Abstract: A standard cell macro embedding method that extends the capability of conventional circuit placement routines by enabling them to automatically and optimally embed macro blocks within standard cell blocks. The macro blocks can be selected portions of the standard cell logic that are extracted and optimized for the purpose of enhancing performance, low power, density or functionality. The present invention optimally places these macros using a two pass placement process in which, first, Anchor and, second, Structure Expansion models of the macro blocks are employed to, respectively, optimally locate the macro blocks, and then, optimally place the standard cells.