Abstract: A flat panel display utilizes an array of eletroluminescent cells in which the active layer is of polycrystalline zinc sulfide that is the host for molecules of a ternary europium fluoride compound, advantageously lithium europium tetrafluoride. Each cell includes a pair of electrodes between which are a silicon dioxide barrier layer, sufficiently thin for electrons to tunnel therethrough, the active layer, and a capacitive dielectric layer. Other ternary europium tetrafluoride compounds are described for use as the active layer.

Abstract: A flat panel display utilizes an array of eletroluminescent cells in which the active layer is of polycrystalline zinc sulfide that is the host for molecules of a ternary europium fluoride compound, advantageously lithium europium tetrafluoride. Each cell includes a pair of electrodes between which are a silicon dioxide barrier layer, sufficiently thin for electrons to tunnel therethrough, the active layer, and a capacitive dielectric layer. Other ternary europium tetrafluoride compounds are discribed for use as the active layer.

Abstract: A complementary MISFET uses gallium antimonide as the active material to utilize the high mobilities of both holes and electrons in such material. To avoid interfacial states at the gate interface, the gate insulator is an epitaxial composite layer formed by an appropriate superlattice of which the portion adjacent the channel region is free of intentional doping. The superlattice may comprise, for example, alternating layers of aluminum antimonide and aluminum arsenide or of aluminum antimonide and gallium arsenide.

Abstract: A semiconductor integrated circuit includes a nitrided silicon dioxide layer typically 50 to 400 Angstroms thick located on a semiconductor medium. The nitrided layer is an original silicon dioxide layer that has been nitrided at its top surface, as by rapid (flash) heating in ammonia to about 1250 degrees C., in such a way that the resulting nitrided silicon dioxide layer is essentially a compound layer of silicon nitroxide on silicon dioxide in which the atomic concentration fraction of nitrogen falls from a value greater than 0.13 at the top surface of the compound layer to a value of about 0.13 within 30 Angstroms or less beneath the top surface, and advantageously to values of less than about 0.05 everywhere at distances greater than about 60 Angstroms or less beneath the top surface, except that the nitrogen fraction can rise to as much as about 0.10 in the layer at distances within about 20 Angstroms from the interface of the nitrided layer and the underlying semiconductor medium.

Abstract: A method of planarizing a surface using ion beam milling at a non-normal angle of incidence that is useful in semiconductor device manufacture is described.

Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Abstract: In the fabrication of semiconductor integrated circuits which include recessed oxide isolation regions (29), formation of the undesired "bird's head" and "bird's beak" is avoided by reducing the rate of oxide growth from the sidewalls of isotropically etched recesses (22) while oxide is being grown from the bottoms of the recess regions. A silicon nitride mask (24) formed selectively on each of the sidewalls which has previously been coated with a thin silicon dioxide layer (23) reduces the rate of oxide growth therefrom, so that the oxidized recess regions have substantially planar surfaces after termination of the oxide growth.

Abstract: A method of making MOS devices, primarily in integrated circuit form, is disclosed. Device areas first are defined on a silicon semiconductor chip, typically by means of a silicon nitride pattern 13A-13B. This pattern then is used to locate impurity introductions and to define areas of semiconductor surface portion removal. The latter operation produces mesas 16-17 coincident with the device areas. By this combination of steps and silicon oxide regrowth 27 where silicon has been removed, well-defined conductivity type zones are formed under the silicon oxide portions to function as buried terminal zones 28, 29, 30 of MOS devices. In the sole critical mask registration step, one edge 38 of the gate electrode 31 is located relative to the boundary 39 of a buried terminal zone 28. Finally, the channel zone 34 and the other terminal zone 33 of an MOS transistor are emplaced by a self-alignment process, followed by a heating step which adjusts final device dimensions.

Abstract: A method for making a metal oxide semiconductor field effect transistor (MOSFET) is disclosed that results in a semiconductor device structure in which the source and drain regions are buried in the structure beneath a typically thick oxide and bulge out in the semiconductor underneath, but not contiguous with, the interface of a typically thin gate oxide with the semiconductor. This bulging of the buried drain, in an N-channel device, results in an electric field profile during operation which curves away from the interface in the neighborhood of the drain, thereby reducing deleterious transport of electrons from the channel to the gate oxide. The method can also be adapted for fabricating integrated memory cell arrays. This adaptation involves the implantation of one or more layers of dopant ions in the region of the semiconductor between the oxide interface and the bulging portion of the buried drain.

Abstract: An SI.sub.1 I.sub.2 M (semiconductor-insulator.sub.1 -insulator.sub.2 -metal) memory structure, containing an impurity such as tungsten concentrated in a region including the interface ("I.sub.1 I.sub.2 ") region between the I.sub.1 and I.sub.2 region, is fabricated by depositing an oxide of the impurity, such as tungsten trioxide, on the then exposed, I.sub.1 layer prior to fabricating the I.sub.2 layer. The oxide of the impurity, such as tungsten trioxide, can be advantageously deposited by means of reactive evaporation.

Abstract: Charge conditions are modified in a wafer including a silicon dioxide layer on a silicon substrate by introducing a distribution of tantalum into the silicon dioxide layer. The distribution of tantalum can be adapted to store negative charge, to getter sodium or to produce nonannealable fast surface states. A distribution of tantalum at the silicon-silicon dioxide interface produces nonannealable fast surface states. A distribution of tantalum in the silicon dioxide subjected to electrical and temperature stress can store negative charge and getter sodium. An n-channel insulated gate field effect transistor utilizes a silicon dioxide gate insulator which includes centrally located therein a region which is rich in treated tantalum.