Patents by Inventor Dax M. CRUM

Dax M. CRUM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12382706
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: August 5, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Patent number: 12369393
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: July 22, 2025
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Publication number: 20250227992
    Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
    Type: Application
    Filed: March 26, 2025
    Publication date: July 10, 2025
    Inventors: Dan S. LAVRIC, Dax M. CRUM, Omair SAADAT, Oleg GOLONZKA, Tahir GHANI
  • Patent number: 12302632
    Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani, Bruce Beattie
  • Patent number: 12295170
    Abstract: Gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer over a second gate dielectric including the high-k dielectric layer on a second dipole material layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Dan S. Lavric, Dax M. Crum, Omair Saadat, Oleg Golonzka, Tahir Ghani
  • Publication number: 20250126832
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Applicant: Intel Corporation
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Patent number: 12224350
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: February 11, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, William Hsu, Leonard P. Guler, Dax M. Crum, Tahir Ghani
  • Publication number: 20240429238
    Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
    Type: Application
    Filed: September 5, 2024
    Publication date: December 26, 2024
    Inventors: Dan S. LAVRIC, Dax M. CRUM, Omair SAADAT, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20240355903
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Biswajeet GUHA, Dax M. CRUM, Stephen M. CEA, Leonard P. GULER, Tahir GHANI
  • Patent number: 12113068
    Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 8, 2024
    Assignee: Intel Corporation
    Inventors: Dan S. Lavric, Dax M. Crum, Omair Saadat, Oleg Golonzka, Tahir Ghani
  • Publication number: 20240332394
    Abstract: Gate-all-around integrated circuit structures having a multi-layer molybdenum metal gate stack are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A PMOS gate stack is over the first vertical arrangement of horizontal nanowires, the PMOS gate stack having a multi-layer molybdenum structure on a first gate dielectric. An NMOS gate stack is over the second vertical arrangement of horizontal nanowires, the NMOS gate stack having the multi-layer molybdenum structure or an N-type conductive layer on a second gate dielectric.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: David N. GOLDSTEIN, David J. TOWNER, Dax M. CRUM, Omair SAADAT, Dan S. LAVRIC, Orb ACTON, Tongtawee WACHARASINDHU, Anand S. MURTHY, Tahir GHANI
  • Publication number: 20240290788
    Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Applicant: Intel Corporation
    Inventors: Guowei Xu, Tao Chu, Chiao-Ti Huang, Robin Chao, David Towner, Orb Acton, Omair Saadat, Feng Zhang, Dax M. Crum, Yang Zhang, Biswajeet Guha, Oleg Golonzka, Anand S. Murthy
  • Publication number: 20240266353
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Application
    Filed: April 2, 2024
    Publication date: August 8, 2024
    Inventors: Dax M. CRUM, Biswajeet GUHA, Leonard GULER, Tahir GHANI
  • Patent number: 12057491
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Dax M. Crum, Stephen M. Cea, Leonard P. Guler, Tahir Ghani
  • Patent number: 12051698
    Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 30, 2024
    Assignee: Intel Corporation
    Inventors: Daniel G. Ouellette, Daniel B. O'Brien, Jeffrey S. Leib, Orb Acton, Lukas Baumgartel, Dan S. Lavric, Dax M. Crum, Oleg Golonzka, Tahir Ghani
  • Publication number: 20240243203
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Patent number: 12002810
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. For example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. The first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. The first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Dax M. Crum, Biswajeet Guha, Leonard Guler, Tahir Ghani
  • Publication number: 20240096896
    Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jun Sung KANG, Kai Loon CHEONG, Erica J. THOMPSON, Biswajeet GUHA, William HSU, Dax M. CRUM, Tahir GHANI, Bruce BEATTIE
  • Publication number: 20240030348
    Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 25, 2024
    Inventors: Biswajeet GUHA, William HSU, Leonard P. GULER, Dax M. CRUM, Tahir GHANI
  • Patent number: 11869891
    Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani, Bruce Beattie