Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.

Abstract: A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.

Abstract: A phase-locked loop (PLL) is provided, which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. The phase detection loop has a loop filter node. A delay element is coupled within the phase detection loop and has a variable delay, which can be increased to a critical delay at which the phase detection loop becomes unstable. A demodulator is coupled to the loop filter node and is adapted to demodulate a modulated voltage on the loop filter node. The demodulator has a demodulated output, which is representative of a phase margin of the phase detection loop when the delay element has the critical delay.