Abstract: Techniques are described for low-noise self-capacitor sensing in a capacitive touch panel array integrated with a display panel. Each channel of the array has a self-capacitance (Ci) that changes responsive to presence or absence of a local touch event local. Each channel is read by an analog front-end (AFE) by using a locally noise-suppressed discharge current for a discrete discharge time to discharge Ci to obtain a discharge voltage level that differs with presence or absence of the local touch event, and outputting a voltage output for the channel based on the discharge voltage level by passively mixing at least the discharge voltage level to produce a pair of up-converted channel signals, sampling the pair of up-converted channel signals to obtain a differential voltage sample, and amplifying the differential voltage sample to generate the Vout as indicating absence or presence of the touch event local to the channel.

Abstract: Techniques are described for using a multi-branch AC-mode bridge approach with global current rotation for self-capacitor sensing in a capacitive touch panel, such as integrated into a display of a touchscreen electronic device. K channels are coupled with K branches of a multi-branch AC-mode bridge to form K?1 pairs of channels for concurrent differential readout. K nominally identical sinusoidal input currents are generated based on an error signal, which is generated based on comparing a sinusoidal driver signal with feedback from one or more of the K branches. A unit current rotator rotates the K sinusoidal input currents to each of the branches, so that each branch current is formed by a rotating contribution from each of the sinusoidal input currents. Driving each branch with its branch current manifests a respective branch voltage, and differences between the branch voltages can be used to differentially sense pairs of channels.

Abstract: Techniques are described for discrete-time self-capacitor sensing in a touch panel. The self-capacitor manifests a detectably different capacitance based on presence or absence of a local touch event on the touch panel. In a first time phase, embodiments charge a self-capacitor and initialize a ramp bias generator. In a second time phase, embodiments discharge the self-capacitor with a ramp-controlled current source that is biased by the ramp bias generator to produce a discharge current that transitions from high at the beginning of the second time phase to low at the end of the second time phase. By the end of the second phase, the remaining charge in the self-capacitor depends on presence or absence of a local touch event. Some embodiments convert the remaining charge to an amplified sense output for readout.

Abstract: Techniques are described for using an alternating-current-mode (AC-mode) bridge for low-noise self-capacitor sensing in a capacitive touch panel array integrated with a display panel. Each channel of the array has a self-capacitance (Ci) that changes responsive to presence or absence of a local touch event local. Pairs of channels are read out differentially by coupling pairs of channels to branches of an AC-mode bridge. The AC-mode bridge includes current sources that drive each branch (and thereby each channel) with a sinusoidal current, manifesting a branch voltage on each branch based on the self-capacitance of the branch. The branch voltages are used to generate an output voltage. The sinusoidal current is controlled by comparing a driver signal with feedback from the branches, so that common-mode noise on the channels becomes a common-mode component of the sinusoidal currents and is rejected in the generation of the output voltage.

Abstract: An image sensor includes image sensor cells generating an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes charge pump cells to receive clock signals and to source charge to the first power supply node, a delay line including delay line elements generating clock signals, where a first charge pump cell receives a first clock signal generated by a first delay line element, where a second charge pump cell receives a second clock signal generated by a second delay line element, and where a delay between the first clock signal and the second clock signal is determined by the delay line.

Abstract: An image sensor includes a plurality of image sensor cells, each configured to generate or not generate an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes a plurality of charge pump cells selectably sourcing charge to the first power supply node in response to one of multiple enable signals, and a charge pump cell quantity controller circuit generating the enable signals. Each enable signal is either in an active or inactive state, and each charge pump cell sources charge to the first power supply node in response to receiving an enable signal in an active state.

Abstract: An image sensor includes image sensor cells, each configured to generate an image signal in response to control signals. The image sensor also includes an ADC to receive the image signals of the image sensor cells, and a first driver to generate one or more first control signals for a first image sensor cell, where the first driver includes a first negative supply terminal. The image sensor also includes a first multiplexor to selectively connect the first negative supply terminal of the first driver to one of a plurality of power supply nodes, and a second driver to generate one or more second control signals for a second image sensor cell, where the second driver includes a second negative supply terminal. The image sensor also includes a second multiplexor to selectively connect the second negative supply terminal of the second driver to one of the power supply nodes.

Abstract: An image sensor includes image sensor cells generating an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes charge pump cells to receive clock signals and to source charge to the first power supply node, a delay line including delay line elements generating clock signals, where a first charge pump cell receives a first clock signal generated by a first delay line element, where a second charge pump cell receives a second clock signal generated by a second delay line element, and where a delay between the first clock signal and the second clock signal is determined by the delay line.

Abstract: An image sensor includes a plurality of image sensor cells, each configured to generate or not generate an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes a plurality of charge pump cells selectably sourcing charge to the first power supply node in response to one of multiple enable signals, and a charge pump cell quantity controller circuit generating the enable signals. Each enable signal is either in an active or inactive state, and each charge pump cell sources charge to the first power supply node in response to receiving an enable signal in an active state.

Abstract: An image sensor includes image sensor cells, each configured to generate an image signal in response to control signals. The image sensor also includes an ADC to receive the image signals of the image sensor cells, and a first driver to generate one or more first control signals for a first image sensor cell, where the first driver includes a first negative supply terminal. The image sensor also includes a first multiplexor to selectively connect the first negative supply terminal of the first driver to one of a plurality of power supply nodes, and a second driver to generate one or more second control signals for a second image sensor cell, where the second driver includes a second negative supply terminal. The image sensor also includes a second multiplexor to selectively connect the second negative supply terminal of the second driver to one of the power supply nodes.

Abstract: An Image sensor includes image sensor cells, each configured to accumulate charge corresponding to light incident thereon, a first driver connected to a power supply node, where the first driver generates control signals for a first image sensor cell based on a voltage of the power supply node, where the first image sensor cell generates an image signal in response to the control signals, and the image signal is based on the accumulated charge of the first image sensor cell. The image sensor also includes an ADC generating a digital representation of the image signal, and a switching voltage generator selectively generating the voltage of the power supply node in response to an enable signal, where the enable signal causes the switching voltage generator to not generate the voltage of the power supply node while the image signal is generated.

Abstract: An integrated circuit includes a plurality of voltage regulators. A given voltage regulator of the plurality of voltage regulators includes a differential amplifier and an output transistor. The differential amplifier and the output transistor are coupled at a gate node of the output transistor. The voltage regulator provides a regulated output voltage at an output node of the output transistor. The integrated circuit includes a common gate line, which is coupled to the gate node of the output transistor in each of the plurality of voltage regulators. The integrated circuit also includes a common power line, which is coupled to the output node of the output transistor in each of the plurality of voltage regulators. The common power line provides operational power to one or more circuit blocks in the integrated circuit.

Abstract: A voltage regulator circuit includes a power supply terminal and a ground terminal, and a differential amplifier coupled between the power supply terminal and the ground terminal. The voltage regulator circuit also includes an output transistor, which includes a gate node coupled to an output node of the differential amplifier to receive a gate voltage and to provide a regulated output voltage at an output node of the output transistor. The differential amplifier is configured to provide the gate voltage based on a differential between a reference voltage and the regulated output voltage. The voltage regulator also includes a compensation capacitance coupled between a virtual ground node in the differential amplifier and either the power supply terminal or the ground terminal and a virtual ground node in the differential amplifier.

Abstract: An integrated circuit includes a plurality of voltage regulators. A given voltage regulator of the plurality of voltage regulators includes a differential amplifier and an output transistor. The differential amplifier and the output transistor are coupled at a gate node of the output transistor. The voltage regulator provides a regulated output voltage at an output node of the output transistor. The integrated circuit includes a common gate line, which is coupled to the gate node of the output transistor in each of the plurality of voltage regulators. The integrated circuit also includes a common power line, which is coupled to the output node of the output transistor in each of the plurality of voltage regulators. The common power line provides operational power to one or more circuit blocks in the integrated circuit.

Abstract: A pulse frequency modulated (PFM) voltage converter autonomously switches between buck, buck-boost, and boost modes as a function of the input and output voltages. The voltage converter may also switch autonomously between buck mode and a low drop out (LDO) mode when configured in a system in which the battery voltage is known to always be higher than the output voltage.

Abstract: A voltage converter includes a comparator that continuously monitors an output voltage of the voltage converter. The comparator includes a first comparator core utilizing first and second switched capacitors and a second comparator core using third and fourth switched capacitors. The first comparator core is powered down or in a refresh mode while the second comparator core is monitoring the output voltage. The second comparator core is powered down or in the refresh mode while the first comparator core is monitoring the output voltage. The first and second switched capacitors are configured in series with an amplifier stage of the first comparator core while the first comparator core is monitoring the output voltage. The refresh mode charges the first (third) and second (fourth) switched capacitors to a scaled version of the output voltage and a reference voltage less an offset voltage, respectively.

Abstract: An apparatus includes a digital battery charger. The digital battery charger includes an analog-to-digital converter (ADC) to convert a terminal voltage of a battery to a first digital signal. The digital battery charger further includes a digital controller coupled to the ADC to receive the first digital signal and provide a set of control signals. The digital battery charger further includes a current digital-to-analog converter (IDAC) coupled to the digital controller to receive the set of control signals and to provide a battery charging current signal.

Abstract: An apparatus includes a voltage regulator to regulate a voltage from a power source and to provide an output current at an output. The apparatus further includes a battery charger, coupled to the voltage regulator, to provide a charge current. The apparatus further includes a controller to control the charge current such that the charge current is less than or equal to a current available from the power source minus the output current.

Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

Abstract: An apparatus includes a voltage regulator to regulate a voltage from a power source and to provide an output current at an output. The apparatus further includes a battery charger, coupled to the voltage regulator, to provide a charge current. The apparatus further includes a controller to control the charge current such that the charge current is less than or equal to a current available from the power source minus the output current.